PIC24FJ64GB004-I/ML Microchip Technology, PIC24FJ64GB004-I/ML Datasheet - Page 222

• Manufacturer Part Number: PIC24FJ64GB004-I/ML
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-44
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ64GB004-I/ML

• Controller Family/series: PIC24
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: I2C, LIN, SPI, UART, USB
• No. Of Pwm Channels: 5
• Core Size: 16 Bit
• Program Memory Size: 64 KB
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Embedded Interface Type: I2C, LIN, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC24FJ64GB004 FAMILY
18.7.2
REGISTER 18-14: U1OTGIR: USB OTG INTERRUPT STATUS REGISTER (HOST MODE ONLY)
DS39940D-page 222
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/K-0, HS
Note:
IDIF
U-0
—
V
USB INTERRUPT REGISTERS
Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the
entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause
all set bits at the moment of the write to become cleared.
BUS
Unimplemented: Read as ‘0’
IDIF: ID State Change Indicator bit
1 = Change in ID state is detected
0 = No ID state change
T1MSECIF: 1 Millisecond Timer bit
1 = The 1 millisecond timer has expired
0 = The 1 millisecond timer has not expired
LSTATEIF: Line State Stable Indicator bit
1 = USB line state (as defined by the SE0 and JSTATE bits) has been stable for 1 ms, but different
0 = USB line state has not been stable for 1 ms
ACTVIF: Bus Activity Indicator bit
1 = Activity on the D+/D- lines or V
0 = No activity on the D+/D- lines or V
SESVDIF: Session Valid Change Indicator bit
1 = V
0 = V
SESENDIF: B-Device V
1 = V
0 = V
Unimplemented: Read as ‘0’
VBUSVDIF A-Device V
1 = V
0 = No V
T1MSECIF
R/K-0, HS
threshold crossings may be either rising or falling.
from last time
OTG Specification)
OTG Specification)
U-0
—
BUS
BUS
BUS
BUS
BUS
BUS
has crossed V
has not crossed V
has not crossed V
change on B-device is detected; V
change on A-device is detected; V
change on A-device is detected
K = Write ‘1’ to clear bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
LSTATEIF
R/K-0, HS
U-0
—
BUS
(1)
(1)
BUS
A
_
SESS
Change Indicator bit
A
Change Indicator bit
A
_
_
SESS
SESS
R/K-0, HS
_
ACTVIF
END
U-0
—
BUS
_
_
END
END
(as defined in the USB OTG Specification)
BUS
is detected
is detected
HS = Hardware Settable bit
‘0’ = Bit is cleared
R/K-0, HS
BUS
SESVDIF
BUS
U-0
—
has crossed V
has crossed V
SESENDIF
R/K-0, HS
U-0
—
B
A
_
_
SESS
VBUS
 2010 Microchip Technology Inc.
_
_
x = Bit is unknown
END
VLD
(as defined in the USB
(as defined in the USB
U-0
U-0
—
—
(1)
VBUSVDIF
R/K-0, HS
U-0
—
bit 8
bit 0