PIC16F886-E/SS Microchip Technology, PIC16F886-E/SS Datasheet - Page 7

• Manufacturer Part Number: PIC16F886-E/SS
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F886-E/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SSOP
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: MSSP, EUSART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM164123, DM164120-3, DV164122
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM164123 - KIT MANAGEMENT SYSTEM PICDEM
• Lead Free Status / Rohs Status: Details

6. Module: MSSP (I
FIGURE 1:
FIGURE 2:
© 2009 Microchip Technology Inc.
SDA
SCL
SDA
SCL
Master
Master
When the MSSP is I
slave device stretching the clock, the clock
generation does not function as described in the
data sheet.
When a slave device is performing clock stretching
by pulling the SCL line low, the master device
should continuously sample the SCL line to
determine when all slaves have released SCL.
When SCL is released, the master device should
wait one BRG period to ensure a constant SCL
high time.
The current implementation does not ensure
accurate SCL high time. During clock stretch, the
MSSP device will erroneously continue running
the BRG counter. At the end of the clock stretch
the BRG counter continues to count down for the
remainder of the BRG period, and then the MSSP
device will immediately resume transmitting the
data.
Slave
Slave
BRG Period
BRG Period
ACTUAL (CORRECT) OPERATION WITHOUT CLOCK STRETCHING
EXPECTED OPERATION WITH CLOCK STRETCHING
2
C™ Master Mode)
2
C™ Master mode with a
BRG Period
BRG Period
BRG Period
BRG Period
BRG Period
Figure 1 illustrates an expected I
in which the SCL line is completely controlled by
the master device and the slave device does not
attempt to stretch the clock period.
Figure 2 illustrates the expected operation of an
I
stretched the clock period by holding the SCL line
low. The high time of the SCL pulse is constant,
regardless of the duration of the clock stretch.
Figure 3 and Figure 4 illustrate an actual I
transmission in which the slave has stretched the
clock period by holding the SCL line low. Note that
the high time of the SCL signal has shortened from
the expected time.
2
C transmission in which the slave device has
BRG Period
PIC16F88X
BRG Period
BRG Period
DS80302F-page 7
2
C transmission
2
C