ISL76683AROZ-T7 Intersil, ISL76683AROZ-T7 Datasheet - Page 6

• Manufacturer Part Number: ISL76683AROZ-T7
• Description: DIGITAL LIGHT SENSOR ADC 6ODFN
• Manufacturer: Intersil

Specifications of ISL76683AROZ-T7

• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Principles of Operation
Photodiodes
The ISL76683 contains two photodiodes. Diode1 is sensitive to
both visible and infrared light, while Diode2 is mostly sensitive to
infrared light. The spectral response of the two diodes are
independent from one another. See Figure 2 “Spectral Response” in
the “Typical Performance Curves” section. The photodiodes
convert light to current then the diodes’ current outputs are
converted to digital by a single built-in integrating type 16-bit
Analog-to-Digital Converter (ADC). An I
determines which photodiode will be converted to a digital signal.
Mode1 is Diode1 only. Mode2 is Diode2 only. Mode3 is a
sequential Mode1 and Mode2 with an internal subtract function
(Diode1 - Diode2).
Analog-to-Digital Converter (ADC)
The converter is a charge-balancing integrating type 16-bit ADC.
The chosen method for conversion is best for converting small
current signals in the presence of AC periodic noise. A 100ms
integration time, for instance, highly rejects 50Hz and 60Hz
power line noise simultaneously. See “Integration Time or
Conversion Time” on page 11 and “Noise Rejection” on page 12.
The built-in ADC offers the user flexibility in integration time or
conversion time. Two timing modes are available; Internal Timing
Mode and External Timing Mode. In Internal Timing Mode,
integration time is determined by an internal dual speed oscillator
(f
External Timing Mode, integration time is determined by the time
between two consecutive I
“External Timing Mode” on page 10. A good balancing act of
integration time and resolution depending on the application is
required for optimal results.
The ADC has four I
dynamically accommodate various lighting conditions. For very
dim conditions, the ADC can be configured at its lowest range.
For very bright conditions, the ADC can be configured at its
highest range.
OSC
), and the n-bit (n = 4, 8, 12, 16) counter inside the ADC. In
2
C programmable range selects to
2
C External Timing Mode commands. See
6
2
C command mode
ISL76683
Interrupt Function
The active low interrupt pin is an open drain pull-down
configuration. The interrupt pin serves as an alarm or monitoring
function to determine whether the ambient light exceeds the
upper threshold or goes below the lower threshold. The user can
also configure the persistency of the interrupt pin. This
eliminates any false triggers, such as noise or sudden spikes in
ambient light conditions. An unexpected camera flash, for
example, can be ignored by setting the persistency to 8
integration cycles.
I
There are eight (8) 8-bit registers available inside the ISL76683. The
command and control registers define the operation of the device.
The command and control registers do not change until the registers
are overwritten. There are two 8-bit registers that set the high and
low interrupt thresholds. There are four 8-bit data Read Only
registers; two bytes for the sensor reading and another two bytes for
the timer counts. The data registers contain the ADC's latest digital
output, and the number of clock cycles in the previous integration
period.
The ISL76683’s I
internally as 1000100. When 1000100x with x as R or W is sent
after the Start condition, this device compares the first seven bits
of this byte to its address and matches.
Figure 12 shows a sample one-byte read. Figure 13 shows a sample
one-byte write. Figure 14 shows a sync_iic timing diagram sample
for externally controlled integration time. The I
drives the SCL (clock) line, while either the master or the slave can
drive the SDA (data) line. Figure 13 shows a sample write. Every I
transaction begins with the master asserting a start condition (SDA
falling while SCL remains high). The following byte is driven by the
master and includes the slave address and read/write bit. The
receiving device is responsible for pulling SDA low during the
acknowledgement period.
Every I
condition (SDA rising while SCL remains high).
For more information about the I
Philips
2
C Interface
2
®
C transaction ends with the master asserting a stop
I
2
C specification documents.
2
C interface slave address is hardwired
2
C standard, please consult the
2
C bus master always
March 17, 2011
FN7697.2
2
C