ISL76683AROZ-T7 Intersil, ISL76683AROZ-T7 Datasheet - Page 9

• Manufacturer Part Number: ISL76683AROZ-T7
• Description: DIGITAL LIGHT SENSOR ADC 6ODFN
• Manufacturer: Intersil

Specifications of ISL76683AROZ-T7

• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Command Register 00(hex)
The Read/Write command register has five functions:
For proper shut down operation, it is recommended to disable
ADC first then disable the chip. Specifically, the user should first
send I
with Bit 6 = 1.
1. Enable; Bit 7. This function either resets the ADC or enables
2. ADCPD; Bit 6. This function puts the device in a power-down
3. Timing Mode; Bit 5. This function determines whether the
b1xxx_xxxx
bx1xx_xxxx
ADDRESS
the ADC in normal operation. A logic 0 disables ADC to reset-
mode. A logic 1 enables ADC to normal operation.
mode. A logic 0 puts the device in normal operation. A logic 1
powers down the device.
integration time is done internally or externally. In Internal
Timing Mode, integration time is determined by an internal dual
speed oscillator (f
inside the ADC. In External Timing Mode, integration time is
determined by the time between two consecutive external-sync
sync_iic pulse commands.
BIT 5
BIT 7
BIT 6
2
0
1
C command with Bit 7 = 0 and then send I
0
1
0
1
Internal Timing Mode. Integration time is internally
timed determined by f
cycles.
External Timing Mode. Integration time is externally
timed by the I
REGISTER
Disable ADC-Core to Reset-Mode (default)
Enable ADC-Core to Normal Operation
Normal Operation (default)
Power-Down
TABLE 2. WRITE ONLY REGISTERS
sync_iic
clar_int
NAME
OSC
TABLE 5. TIMING MODE
TABLE 3. ENABLE
), and the n-bit (n = 4, 8, 12,16) counter
TABLE 4. ADCPD
2
Writing a logic 1 to this address bit ends
the current ADC-integration and starts
another. Used only with External Timing
Mode.
Writing a logic 1 to this address bit clears
the interrupt.
C host.
9
OPERATION
OSC
OPERATION
OPERATION
, REXT, and number of clock
DESCRIPTION
FUNCTIONS/
2
C command
ISL76683
*n = 4, 8, 12,16 depending on the number of clock cycles
function.
Control Register 01(hex)
The Read/Write control register has three functions:
4. Photodiode Select Mode; Bits 3 and 2. This function controls
5. Width; Bits 1 and 0. This function determines the number of
1. Interrupt flag; Bit 5. This is the status bit of the interrupt. The
BITS 3:2
the mux attached to the two photodiodes. At Mode1, the mux
directs the current of Diode1 to the ADC. At Mode2, the mux
directs the current of Diode2 only to the ADC. Mode3 is a
sequential Mode1 and Mode2 with an internal subtract
function (Diode1 - Diode2).
clock cycles per conversion. Changing the number of clock
cycles does more than just change the resolution of the
device; it also changes the integration time, which is the
period the device’s analog-to-digital (A/D) converter samples
the photodiode current signal for a lux measurement.
bit is set to logic high when the interrupt thresholds have been
triggered, and logic low when not yet triggered. Writing a logic
low clears/resets the status bit.
BITS 1:0
0:0
0:1
1:0
1:1
BIT 5
0:0
0:1
1:0
1:1
0
1
TABLE 6. PHOTODIODE SELECT MODE; BITS 2 AND 3
MODE1. ADC integrates or converts Diode1 only. Current
is converted to an n-bit unsigned data.*
MODE2. ADC integrates or coverts Diode2 only. Current is
converted to an n-bit unsigned data.*
MODE3. A sequential MODE1 then MODE2 operation.
The difference current is an (n-1) signed data.*
No Operation.
2
2
2
2
Interrupt is cleared or not triggered yet
Interrupt is triggered
16
12
4
8
= 256
= 16
TABLE 8. INTERRUPT FLAG
= 65,536
= 4,096
TABLE 7. WIDTH
NUMBER OF CLOCK CYCLES
OPERATION
MODE
March 17, 2011
FN7697.2