MFRC52302HN1,151 NXP Semiconductors, MFRC52302HN1,151 Datasheet - Page 94

• Manufacturer Part Number: MFRC52302HN1,151
• Description: IC READER 32-HVQFN
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC52302HN1,151

• Rf Type: Read / Write
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935293911151

NXP Semiconductors
Table 69. RxSelReg register bit descriptions . . . . . . . . . .50
Table 70. RxThresholdReg register (address 18h); reset
Table 71. RxThresholdReg register bit descriptions . . . .51
Table 72. DemodReg register (address 19h); reset value:
Table 73. DemodReg register bit descriptions . . . . . . . . .51
Table 74. Reserved register (address 1Ah); reset value: 00h
Table 75. Reserved register bit descriptions . . . . . . . . . .52
Table 76. Reserved register (address 1Bh); reset value: 00h
Table 77. Reserved register bit descriptions . . . . . . . . . .52
Table 78. MfTxReg register (address 1Ch); reset value: 62h
Table 79. MfTxReg register bit descriptions . . . . . . . . . .53
Table 80. MfRxReg register (address 1Dh); reset value: 00h
Table 81. MfRxReg register bit descriptions . . . . . . . . . .53
Table 82. TypeBReg register (address 1Eh); reset value:
Table 83. TypeBReg register bit descriptions . . . . . . . . .53
Table 84. SerialSpeedReg register (address 1Fh); reset
Table 85. SerialSpeedReg register bit descriptions . . . . .54
Table 86. Reserved register (address 20h); reset value: 00h
Table 87. Reserved register bit descriptions . . . . . . . . . .55
Table 88. CRCResultReg (higher bits) register (address
Table 89. CRCResultReg register higher bit descriptions 55
Table 90. CRCResultReg (lower bits) register (address
Table 91. CRCResultReg register lower bit descriptions .55
Table 92. Reserved register (address 23h); reset value: 88h
Table 93. Reserved register bit descriptions . . . . . . . . . .56
Table 94. ModWidthReg register (address 24h); reset value:
Table 95. ModWidthReg register bit descriptions . . . . . .56
Table 96. Reserved register (address 25h); reset value: 87h
Table 97. Reserved register bit descriptions . . . . . . . . . .56
Table 98. RFCfgReg register (address 26h); reset value:
Table 99. RFCfgReg register bit descriptions . . . . . . . . .57
Table 100. GsNReg register (address 27h); reset value: 88h
Table 101. GsNReg register bit descriptions . . . . . . . . . .57
Table 102. CWGsPReg register (address 28h); reset value:
MFRC523
Product data sheet
COMPANY PUBLIC
value: 84h bit allocation . . . . . . . . . . . . . . . . . .51
4Dh bit allocation . . . . . . . . . . . . . . . . . . . . . . .51
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .52
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .52
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .52
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .53
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . .53
value: EBh bit allocation . . . . . . . . . . . . . . . . .54
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .55
21h); reset value: FFh bit allocation . . . . . . . .55
22h); reset value: FFh bit allocation . . . . . . . .55
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .56
26h bit allocation . . . . . . . . . . . . . . . . . . . . . . .56
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .56
48h bit allocation . . . . . . . . . . . . . . . . . . . . . . .57
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .57
20h bit allocation . . . . . . . . . . . . . . . . . . . . . . .58
All information provided in this document is subject to legal disclaimers.
Rev. 3.7 — 8 November 2011
115237
Table 103. CWGsPReg register bit descriptions . . . . . . . 58
Table 104. ModGsPReg register (address 29h); reset value:
Table 105. ModGsPReg register bit descriptions . . . . . . . 58
Table 106. TModeReg register (address 2Ah); reset value:
Table 107. TModeReg register bit descriptions . . . . . . . . 59
Table 108. TPrescalerReg register (address 2Bh); reset
Table 109. TPrescalerReg register bit descriptions . . . . . 60
Table 110. TReloadReg (higher bits) register (address 2Ch);
Table 111. TReloadReg register higher bit descriptions . . 60
Table 112. TReloadReg (lower bits) register (address 2Dh);
Table 113. TReloadReg register lower bit descriptions . . 60
Table 114. TCounterValReg (higher bits) register (address
Table 115. TCounterValReg register higher bit
Table 116. TCounterValReg (lower bits) register (address
Table 117. TCounterValReg register lower bit
Table 118. Reserved register (address 30h); reset value: 00h
Table 119. Reserved register bit descriptions . . . . . . . . . 61
Table 120. TestSel1Reg register (address 31h); reset value:
Table 121. TestSel1Reg register bit descriptions . . . . . . . 61
Table 122. TestSel2Reg register (address 32h); reset value:
Table 123. TestSel2Reg register bit descriptions . . . . . . . 62
Table 124. TestPinEnReg register (address 33h); reset
Table 125. TestPinEnReg register bit descriptions . . . . . 62
Table 126. TestPinValueReg register (address 34h); reset
Table 127. TestPinValueReg register bit descriptions . . . 63
Table 128. TestBusReg register (address 35h); reset value:
Table 129. TestBusReg register bit descriptions . . . . . . . 63
Table 130. AutoTestReg register (address 36h); reset value:
Table 131. AutoTestReg register bit descriptions . . . . . . . 64
Table 132. VersionReg register (address 37h); reset value:
Table 133. VersionReg register bit descriptions . . . . . . . . 64
Table 134. AnalogTestReg register (address 38h); reset
Table 135. AnalogTestReg register bit descriptions . . . . . 65
20h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 58
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 58
value: 00h bit allocation . . . . . . . . . . . . . . . . . 59
reset value: 00h bit allocation . . . . . . . . . . . . . 60
reset value: 00h bit allocation . . . . . . . . . . . . . 60
2Eh); reset value: xxh bit allocation . . . . . . . . 60
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2Fh); reset value: xxh bit allocation . . . . . . . . 61
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 61
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 61
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 62
value: 80h bit allocation . . . . . . . . . . . . . . . . . 62
value: 00h bit allocation . . . . . . . . . . . . . . . . . 63
xxh bit allocation . . . . . . . . . . . . . . . . . . . . . . . 63
40h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 63
xxh bit allocation . . . . . . . . . . . . . . . . . . . . . . . 64
value: 00h bit allocation . . . . . . . . . . . . . . . . . 64
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MFRC523
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