AD7791BRM Analog Devices Inc, AD7791BRM Datasheet - Page 11

• Manufacturer Part Number: AD7791BRM
• Description: Low Power 16-Bit SD ADC I.C.
• Manufacturer: Analog Devices Inc

Specifications of AD7791BRM

• Rohs Status: RoHS non-compliant
• Number Of Bits: 24
• Sampling Rate (per Second): 120
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 230µW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

STATUS REGISTER (RS1, RS0 = 0, 0; POWER-ON/RESET = 0x8C)
The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register,
select the next operation to be a read, and load bits RS1 and RS0 with 0. Table 8 outlines the bit designations for the status register. SR0
through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data stream. The
number in brackets indicates the power-on/reset default status of that bit.
SR7
RDY(1)
Table 8. Status Register Bit Designations
Bit Location
SR7
SR6
SR5
SR4
SR3
SR2
SR1–SR0
MODE REGISTER (RS1, RS0 = 0, 1; POWER-ON/RESET = 0x02)
The mode register is an 8-bit register from which data can be read or to which data can be written. This register is used to configure the
ADC for unipolar or bipolar mode, enable or disable the buffer, or place the device into power-down mode. Table 9 outlines the bit desig-
nations for the mode register. MR0 through MR7 indicate the bit locations, MR denoting the bits are in the mode register. MR7 denotes
the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. Any write to the setup regis-
ter resets the modulator and filter and sets the RDY bit.
MR7
MD1(0)
Table 9. Mode Register Bit Designations
Bit Location
MR7–MR6
MR5–MR4
SR6
ERR(0)
MR6
MD0(0)
Bit Name
RDY
ERR
0
0
1
1
CH1–CH0
Bit Name
MD1–MD0
0
Description
Ready bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically
after the ADC data register has been read or a period of time before the data register is updated with a
new conversion result to indicate to the user not to read the conversion data. It is also set when the part
is placed in power-down mode. The end of a conversion is indicated by the DOUT/RDY pin also. This pin
can be used as an alternative to the status register for monitoring the ADC for conversion data.
ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written
to the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange,
underrange. Cleared by a write operation to start a conversion.
This bit is automatically cleared.
This bit is automatically cleared.
This bit is automatically set.
This bit is automatically set if the device is an AD7791. It can be used to distinguish between the AD7791
and AD7790, in which the bit is cleared.
These bits indicate which channel is being converted by the ADC.
Description
Mode Select Bits. These bits select between continuous conversion mode, single conversion mode, and
standby mode. In continuous conversion mode, the ADC continuously performs conversions and places
the result in the data register. RDY goes low when a conversion is complete. The user can read these
conversions by placing the device in continuous read mode whereby the conversions are automatically
placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to
output the conversion by writing to the communications register. After power-on, the first conversion is
available after a period 2/ f
conversion mode, the ADC is placed in power-down mode when conversions are not being performed.
When single conversion mode is selected, the ADC powers up and performs a single conversion, which
occurs after a period 2/f
ADC returns to power-down mode. The conversion remains in the data register and RDY remains active
(low) until the data is read or another conversion is performed. See Table 10.
This bit must be programmed with a Logic 0 for correct operation.
SR5
0(0)
MR5
0(0)
SR4
0(0)
MR4
0(0)
ADC
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. The conversion result in placed in the data register, RDY goes low, and the
ADC
while subsequent conversions are available at a frequency of f
SR3
1(1)
MR3
BO(0)
SR2
WL(1)
MR2
U/B(0)
SR1
CH1(0)
MR1
BUF(1)
SR0
CH0(0)
MR0
0(0)
ADC
AD7791
. In single