AD7791BRM Analog Devices Inc, AD7791BRM Datasheet - Page 5

• Manufacturer Part Number: AD7791BRM
• Description: Low Power 16-Bit SD ADC I.C.
• Manufacturer: Analog Devices Inc

Specifications of AD7791BRM

• Rohs Status: RoHS non-compliant
• Number Of Bits: 24
• Sampling Rate (per Second): 120
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 230µW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TIMING CHARACTERISTICS
Table 2. (V
Input Logic 1 = V
Parameter
t
t
Read Operation
t
t
t
t
t
Write Operation
t
t
t
t
1
2
3
4
5
6
3
4
1
2
5
6
7
8
9
10
11
Sample tested during initial release to ensure compliance. All input signals are specified with t
See Figure 3 and Figure 4.
These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the V
SCLK active edge is falling edge of SCLK.
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.
RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high,
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
only once.
3
5, 6
DD
= 2.5 V to 5.25 V; GND = 0 V, REFIN(+) = 2.5 V, REFIN(–) = GND, CDIV1 = CDIV0 = 0, Input Logic 0 = 0 V,
DD
, unless otherwise noted.)
Limit at T
(B Version)
100
100
0
60
80
0
60
80
10
80
100
10
0
30
25
0
MIN
1, 2
, T
MAX
Unit
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns max
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
Rev. 0 | Page 5 of 20
R
= t
F
= 5 ns (10% to 90% of V
Conditions/Comments
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS Falling Edge to DOUT/RDY Active Time
V
V
SCLK Active Edge to Data Valid Delay
V
V
Bus Relinquish Time after CS Inactive Edge
SCLK Inactive Edge to CS Inactive Edge
SCLK Inactive Edge to DOUT/RDY High
CS Falling Edge to SCLK Active Edge Setup Time
Data Valid to SCLK Edge Setup Time
Data Valid to SCLK Edge Hold Time
CS Rising Edge to SCLK Edge Hold Time
DD
DD
DD
DD
= 4.75 V to 5.25 V
= 2.5 V to 3.6 V
= 4.75 V to 5.25 V
= 2.5 V to 3.6 V
DD
OL
) and timed from a voltage level of 1.6 V.
or V
OH
limits.
4
AD7791
4