ADA4927-1YCPZ-RL Analog Devices Inc, ADA4927-1YCPZ-RL Datasheet - Page 7

UltraLw Distortion Crnt Fdbck ADC Driver

ADA4927-1YCPZ-RL

Manufacturer Part Number
ADA4927-1YCPZ-RL
Description
UltraLw Distortion Crnt Fdbck ADC Driver
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADA4927-1YCPZ-RL

Amplifier Type
Current Feedback
Number Of Circuits
1
Output Type
Differential
Slew Rate
5000 V/µs
-3db Bandwidth
2.3GHz
Current - Input Bias
500nA
Voltage - Input Offset
300µV
Current - Supply
20mA
Current - Output / Channel
65mA
Voltage - Supply, Single/dual (±)
4.5 V ~ 11 V, ±2.25 V ~ 5.5 V
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
16-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Gain Bandwidth Product
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter
Supply Voltage
Power Dissipation
Input Currents +IN, −IN, PD
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ
to a high thermal conductivity 2s2p circuit board, as described
in EIA/JESD 51-7.
Table 8.
Package Type
16-Lead LFCSP (Exposed Pad)
24-Lead LFCSP (Exposed Pad)
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4927 package
is limited by the associated rise in junction temperature (T
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the ADA4927. Exceeding a junction temperature
of 150°C for an extended period can result in changes in the
silicon devices, potentially causing failure.
JA
is specified for the device (including exposed pad) soldered
Rating
11 V
See Figure 4
±5 mA
−65°C to +125°C
−40°C to +105°C
300°C
150°C
θ
87
47
JA
Unit
°C/W
°C/W
J
) on
Rev. A | Page 7 of 24
The power dissipated in the package (P
quiescent power dissipation and the power dissipated in the
package due to the load drive. The quiescent power is the voltage
between the supply pins (V
The power dissipated due to the load drive depends upon the
particular application. The power due to load drive is calculated
by multiplying the load current by the associated voltage drop
across the device. RMS voltages and currents must be used in
these calculations.
Airflow increases heat dissipation, effectively reducing θ
addition, more metal directly in contact with the package leads/
exposed pad from metal traces, throughholes, ground, and power
planes reduces θ
Figure 4 shows the maximum safe power dissipation in the package
vs. the ambient temperature for the single 16-lead LFCSP (87°C/W)
and the dual 24-lead LFCSP (47°C/W) on a JEDEC standard
4-layer board with the exposed pad soldered to a PCB pad that
is connected to a solid plane.
ESD CAUTION
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–40
Ambient Temperature for a 4-Layer Board
Figure 4. Maximum Power Dissipation vs.
–20
JA
.
AMBIENT TEMPERATURE (°C)
0
ADA4927-1
S
ADA4927-1/ADA4927-2
) times the quiescent current (I
20
ADA4927-2
40
D
) is the sum of the
60
80
100
JA
. In
S
).

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