ADSP-2191MBSTZ-140 Analog Devices Inc, ADSP-2191MBSTZ-140 Datasheet - Page 36

• Manufacturer Part Number: ADSP-2191MBSTZ-140
• Description: IC,DSP,16-BIT,CMOS,QFP,144PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2191MBSTZ-140

• Interface: Host Interface, SPI, SSP, UART
• Clock Rate: 140MHz
• Non-volatile Memory: External
• On-chip Ram: 160kB
• Voltage - I/o: 3.00V, 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 16b
• Clock Freq (max): 140MHz
• Mips: 140
• Device Input Clock Speed: 140MHz
• Ram Size: 160KB
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (min): 2.37/2.97V
• Operating Supply Voltage (max): 2.63/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP-2191MBSTZ140

ADSP-2191M
Serial Peripheral Interface (SPI) Port—Master Timing
Table 20
Table 20. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Switching Characteristics
t
t
t
t
t
t
t
t
Timing Requirements
t
t
SDSCIM
SPICHM
SPICLM
SPICLK
HDSM
SPITDM
DDSPID
HDSPID
SSPID
HSPID
and
CPHA = 1
CPHA = 0
(CPOL = 1)
(CPOL = 0)
(x = 0 or 1)
(OUTPUT)
(OUTPUT)
(OUTPUT)
Figure 21
(OUTPUT)
SPIxSEL
(OUTPUT)
(INPUT)
(INPUT)
SCLK
SCLK
SPIxSEL Low to First SCLK edge (x=0 or 1)
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
Last SCLK Edge to SPIxSEL High (x=0 or 1)
Sequential Transfer Delay
SCLK Edge to Data Output Valid (Data Out Delay)
SCLK Edge to Data Output Invalid (Data Out Hold)
Data Input Valid to SCLK Edge (Data Input Setup)
SCLK Sampling Edge to Data Input Invalid (Data In Hold)
MISO
MISO
MOSI
MOSI
describe SPI port master operations.
t
SSPID
t
SDSCIM
t
SPICLM
Figure 21. Serial Peripheral Interface (SPI) Port—Master Timing
t
VALID
SSPID
MSB
t
SPICHM
MSB
VALID
t
MSB
HSPID
t
SPICLM
t
MSB
DDSPID
t
HSPID
t
DDSPID
t
SPICHM
–36–
t
HDSPID
VALID
t
t
LSB
SPICLK
SSPID
t
HDSPID
LSB
VALID
LSB
Min
2t
2t
2t
4t
2t
2t
0
0
8
1
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
t
HDSM
LSB
–3
–3
–3
–1
–3
–2
t
HSPID
t
SPITDM
Max
6
5
REV. A
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns