ADSP-21992BSTZ Analog Devices Inc, ADSP-21992BSTZ Datasheet - Page 31

• Manufacturer Part Number: ADSP-21992BSTZ
• Description: Mixed Signal DSP W/32K DM RAM& 16K PMRAM
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-21992BSTZ

• Interface: SPI, SSP
• Clock Rate: 160MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Clock In and Clock Out Cycle Timing
Table 17
binations of CLKIN and clock multipliers must not select
core/peripheral clocks in excess of 160 MHz/80 MHz for the
ADSP-21992BST, 150 MHz/75 MHz for both the
ADSP-21992BBC and ADSP-21992YBC, and 100 MHz/50 MHz
for the ADSP-21992YST, when the peripheral clock rate is one-
Table 17. Clock In and Clock Out Cycle Timing
1
2
3
In clock multiplier mode and MSEL6–0 set for 1:1 (or CLKIN = CCLK), t
In bypass mode, t
CLKOUT jitter can be as great as 8 ns when CLKOUT frequency is less than 20 MHz. For frequencies greater than 20 MHz, jitter is less than 1 ns.
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
Switching Characteristics
t
t
CK
CKL
CKH
WRST
MSS
MSH
MSD
PFD
CKOD
CKO
and
Figure 7
CK
= t
CCLK
CLKIN Period
CLKIN Low Pulse
CLKIN High Pulse
RESET Asserted Pulse Width Low
MSELx/BYPASS Stable Before RESET Deasserted Setup
MSELx/BYPASS Stable After RESET Deasserted Hold
MSELx/BYPASS Stable After RESET Asserted
Flag Output Disable Time After RESET Asserted
CLKOUT Delay from CLKIN
CLKOUT Period
describe clock and reset operations. Com-
.
1, 2
3
Rev. A | Page 31 of 60 | August 2007
CK
= t
CCLK
.
half the core clock rate. If the peripheral clock rate is equal to the
core clock rate, the maximum peripheral clock rate is 80 MHz
for the ADSP-21992BST, 75 MHz for ADSP-21992BBC and
ADSP-21992YBC, and 50 MHz for the ADSP-21992YST. The
peripheral clock is supplied to the CLKOUT pins.
When changing from bypass mode to PLL mode, allow 512
HCLK cycles for the PLL to stabilize.
Min
10
4.5
4.5
200t
40
1000
0
12.5
CLKOUT
Max
200
200
10
5.8
ADSP-21992
Unit
ns
ns
ns
ns
μs
ns
ns
ns
ns
ns