CS8421-DZZR Cirrus Logic Inc, CS8421-DZZR Datasheet - Page 17

• Manufacturer Part Number: CS8421-DZZR
• Description: IC,Digital Audio Sample Rate Converter,CMOS,TSSOP,20PIN
• Manufacturer: Cirrus Logic Inc

6.7
The CS8421 uses the clock signal supplied through XTI as its master clock (MCLK). MCLK can be sup-
plied from a digital clock source, a crystal oscillator, or a fundamental mode crystal. Figure 10 shows the
typical connection diagram for using a fundamental mode crystal. Please refer to the crystal manufactur-
er’s specifications for the external capacitor recommendations. If XTO is not used, such as with a digital
clock source or crystal oscillator, XTO should be left unconnected or pulled low through a 47 kΩ resistor
to GND.
If either serial audio port is set as master, MCLK will be used to supply the sub-clocks to the master SCLK
and LRCK. In this case MCLK will be synchronous to the master serial audio port. If both serial audio ports
are set as slave, MCLK can be asynchronous to either or both ports. If the user needs to change the clock
source to XTI while the CS8421 is still powered on and running, a RESET must be issued once the XTI
clock source is present and valid to ensure proper operation.
When both serial ports are configured as slave and operating at sample rates less than 96 kHz, the
CS8421 has the ability to operate without a master clock input through XTI. This benefits the design by
not requiring extra external clock components (lowering production cost) and not requiring a master clock
to be routed to the CS8421, resulting in lowered noise contribution in the system. In this mode, an internal
oscillator provides the clock to run all of the internal logic. To enable the internal oscillator simply tie XTI
to GND or VL. In this mode, XTO should be left unconnected.
The CS8421 can also provide a buffered MCLK output through the MCLK_OUT pin. This pin can be used
to supply MCLK to other system components that operate synchronously to MCLK. If MCLK_OUT is not
needed, the output of the pin can be disabled by pulling the pin high through a 47 kΩ resistor to VL.
MCLK_OUT is also disabled when using the internal oscillator mode. The MCLK_OUT pin will be set low
when disabled by using the internal oscillator mode.
DS641PP1
Master Clock
Figure 10. Typical Connection Diagram for Crystal Circuit
XTI
C
XTO
R
C
CS8421
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