CS8421-DZZR Cirrus Logic Inc, CS8421-DZZR Datasheet - Page 18

• Manufacturer Part Number: CS8421-DZZR
• Description: IC,Digital Audio Sample Rate Converter,CMOS,TSSOP,20PIN
• Manufacturer: Cirrus Logic Inc

6.8
TDM mode allows several CS8421 to be serially connected together allowing their corresponding SDOUT
data to be multiplexed onto one line for input into a DSP or other TDM capable multichannel device.
The CS8421 can operate in two TDM modes. The first mode consists of all of the CS8421’s output ports
set to slave as shown in Figure 13. The second mode consists of one CS8421 output port set to master
and the remaining CS8421’s output ports set to slave as shown in Figure 14.
The TDM_IN pin is used to input the data while the SDOUT pin is used to output the data. The first
CS8421 in the chain should have its TDM_IN set to GND. Data is transmitted from SDOUT most signifi-
cant bit first on the first OSCLK after an OLRCK transition and is valid on the rising edge of OSCLK.
In TDM slave mode, the number of channels that can by multiplexed to one serial data line depends on
the output sampling rate. For slave mode, OSCLK must operate at N*64*Fso, where N is the number of
CS8421’s connected together. The maximum allowable OSCLK frequency is 24.576 MHz, so for Fso =
48 kHz, N = 8 (16 channels of serial audio data).
In TDM master mode, OSCLK operates at 256*Fso, which is equivalent to N = 4, so a maximum of 8 chan-
nels of digital audio can be multiplexed together. Note that for TDM master mode, MCLK must be at least
256*Fso, where Fso ≤ 96 kHz. OLRCK identifies the start of a new frame. Each time slot is 32-bits wide,
with the valid data sample left justified within the time slot. Valid data lengths are 16, 20, 24 or 32-bits.
Figure 11 and Figure 12 show the interface format for master and slave TDM modes.
18
SDOUT/
TDM_IN
SDOUT/
TDM_IN
OLRCK
OSCLK
OLRCK
OSCLK
Time Division Multiplexing (TDM) Mode
MSB
MSB
Channel1
Channel1
32 clks
32 clks
LSB
LSB
MSB
MSB
Channel2
Channel2
32 clks
32 clks
Figure 12. TDM Master Mode Timing Diagram
Figure 11. TDM Slave Mode Timing Diagram
LSB
LSB
MSB
MSB
Channel3
Channel3
32 clks
32 clks
LSB
LSB
MSB
MSB
Channel4
Channel4
32 clks
32 clks
256 clks
LSB
LSB
MSB
MSB
Channel5
Channel5
32 clks
32 clks
LSB
LSB
MSB
MSB
Channel6
Channel6
32 clks
32 clks
LSB
LSB
MSB
MSB
Channel7
Channel7
32 clks
32 clks
LSB
LSB
CS8421
MSB
MSB
DS641PP1
Channel8
Channel8
32 clks
32 clks
LSB
LSB