CY7C1356C-166BGC Cypress Semiconductor Corp, CY7C1356C-166BGC Datasheet - Page 22

• Manufacturer Part Number: CY7C1356C-166BGC
• Description: SRAM (Static RAM)
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1356C-166BGC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (512K x 18)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 119-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Switching Characteristics
Over the Operating Range
Document Number: 38-05538 Rev. *L
t
Clock
t
F
t
t
t
t
Output Times
t
t
t
t
t
t
t
Setup Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
Notes
Power
CYC
CH
CL
EOV
CLZ
CO
EOV
DOH
CHZ
CLZ
EOHZ
EOLZ
AS
DS
CENS
WES
ALS
CES
AH
DH
CENH
WEH
ALH
CEH
22. Timing reference level is 1.5 V when V
23. Test conditions shown in (a) of
24. This part has a voltage regulator internally; t
25. t
26. At any given voltage and temperature, t
27. This parameter is sampled and not 100% tested.
MAX
Parameter
initiated.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve high Z prior to low Z under the same system conditions.
CHZ
[24]
, t
CLZ
, t
EOLZ
, and t
V
Clock cycle time
Maximum operating frequency
Clock HIGH
Clock LOW
OE LOW to output valid
Clock to low Z
Data output valid after CLK rise
OE LOW to output valid
Data output hold after CLK rise
Clock to high Z
Clock to low Z
OE HIGH to output high Z
OE LOW to output low Z
Address setup before CLK rise
Data input setup before CLK rise
CEN setup before CLK rise
WE, BW
ADV/LD setup before CLK rise
Chip select setup
Address hold after CLK rise
Data input hold after CLK rise
CEN hold after CLK rise
WE , BW
ADV/LD hold after CLK rise
Chip select hold after CLK rise
CC
(typical) to the first access read or write
EOHZ
x
x
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
setup before CLK rise
hold after CLK rise
[22, 23]
Figure 4 on page 21
[25, 26, 27]
[25, 26, 27]
[25, 26, 27]
Description
DDQ
EOHZ
= 3.3 V and is 1.25 V when V
power
is less than t
[25, 26, 27]
is the time power needs to be supplied above V
[25, 26, 27]
unless otherwise noted.
EOLZ
and t
CHZ
is less than t
DDQ
= 2.5 V.
1.25
1.25
1.25
1.25
Min
4.0
1.8
1.8
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
1
–
–
–
–
–
0
–250
CLZ
to eliminate bus contention between SRAMs when sharing the same
Max
250
2.8
2.8
2.8
2.8
2.8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DD
minimum initially, before a Read or Write operation can be
Min
2.0
2.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
5
–
–
–
–
–
0
–200
CY7C1354C, CY7C1356C
Max
200
3.2
3.2
3.2
3.2
3.2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Min
1.5
1.5
1.5
0.5
2.4
2.4
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
1
6
–
–
–
0
–
–
–166
Max
166
3.5
3.5
3.5
3.5
3.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Page 22 of 32
Unit
MHz
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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