CY7C1357C-100AXCT Cypress Semiconductor Corp, CY7C1357C-100AXCT Datasheet - Page 10

• Manufacturer Part Number: CY7C1357C-100AXCT
• Description: CY7C1357C-100AXCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1357C-100AXCT

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (512K x 18)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Definitions
Functional Overview
The CY7C1355C/CY7C1357C is a synchronous flow-through
burst SRAM designed specifically to eliminate wait states during
write-read transitions. All synchronous inputs pass through input
registers controlled by the rising edge of the clock. The clock
signal is qualified with the clock enable input signal (CEN). If
CEN is HIGH, the clock signal is not recognized and all internal
states are maintained. All synchronous operations are qualified
with CEN. Maximum access delay from the clock rise (t
6.5 ns (133-MHz device).
Accesses can be initiated by asserting all three chip enables
(CE
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BW
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
should be driven LOW once the device has been deselected in
order to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
and CE
WE is deasserted HIGH, and 4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
address register and presented to the memory array and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the
output buffers. The data is available within 7.5 ns (133-MHz
device) provided OE is active LOW. After the first clock of the
read access, the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW in order for the
device to drive out the requested data. On the subsequent clock,
another operation (read/write/deselect) can be initiated. When
the SRAM is deselected at clock rise by one of the chip enable
signals, its output will be tri-stated immediately.
Document Number: 38-05539 Rev. *H
TMS
TCK
NC
V
SS
1
/DNU
, CE
Name
3
are all asserted active, (3) the write enable input signal
2
, CE
3
) active at the rising edge of the clock. If clock
JTAG serial input
Ground/DNU
synchronous
(continued)
JTAG
clock
I/O
–
X
can be used to conduct byte write
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not being utilized, this pin can be disconnected or connected to V
available on TQFP packages.
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
be connected to V
No connects. Not internally connected to the die. 18-Mbit, 36-Mbit, 72-Mbit, 144-Mbit,
288-Mbit, 576-Mbit and 1-Gbit are address expansion pins and are not internally connected
to the die.
This pin can be connected to Ground or should be left floating.
1
, CE
2
, CE
3
) and an
SS
1
CDV
, CE
. This pin is not available on TQFP packages.
) is
2
,
Burst Read Accesses
The CY7C1355C/CY7C1357C has an on-chip burst counter that
allows the user the ability to supply a single address and conduct
up to four reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the
above. The sequence of the burst counter is determined by the
MODE input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both burst
counters use A0 and A1 in the burst sequence, and will wrap
around when incremented sufficiently. A HIGH input on ADV/LD
will increment the internal burst counter regardless of the state
of chip enable inputs or WE. WE is latched at the beginning of a
burst cycle. Therefore, the type of access (read or write) is
maintained throughout the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
and CE
asserted LOW. The address presented to the address bus is
loaded into the address register. The write signals are latched
into the control logic block. The data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQs and DQP
On the next clock rise the data presented to DQs and DQP
a subset for byte write operations, see Truth Table for details)
inputs is latched into the device and the write is complete.
Additional accesses (read/write/deselect) can be initiated on this
cycle.
The data written during the write operation is controlled by BW
signals. The CY7C1355C/CY7C1357C provides byte write
capability that is described in the Truth Table. Asserting the write
enable input (WE) with the selected byte write select input will
selectively write to only the desired bytes. Bytes not selected
during a byte write operation will remain unaltered. A
synchronous self-timed write mechanism has been provided to
simplify the Write operations. Byte write capability has been
included
sequences, which can be reduced to simple byte write
operations.
Because the CY7C1355C/CY7C1357C is a common I/O device,
data should not be driven into the device while the outputs are
active. The output enable (OE) can be deasserted HIGH before
presenting data to the DQs and DQP
Description
3
are all asserted active, and (3) the write signal WE is
in
order
CY7C1355C, CY7C1357C
to
greatly
Single Read Accesses
DD
simplify
. This pin is not
X
inputs. Doing so will
read/modify/write
Page 10 of 32
section
1
, CE
X
(or
X
2
X
[+] Feedback
,
.