CY7C1357C-100AXCT Cypress Semiconductor Corp, CY7C1357C-100AXCT Datasheet - Page 15

• Manufacturer Part Number: CY7C1357C-100AXCT
• Description: CY7C1357C-100AXCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1357C-100AXCT

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (512K x 18)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required—that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
TAP Timing
TAP AC Switching Characteristics
Over the Operating Range
Document Number: 38-05539 Rev. *H
Clock
t
t
t
t
Output Times
t
t
Set-up Times
t
t
t
Hold Times
t
t
t
Notes
Parameter
TCYC
TF
TH
TL
TDOV
TDOX
TMSS
TDIS
CS
TMSH
TDIH
CH
10. t
11. Test conditions are specified using the load in TAP AC Test Conditions. t
CS
and t
CH
refer to the set-up and hold time requirements of latching data from the boundary scan register.
TCK clock cycle time
TCK clock frequency
TCK clock HIGH time
TCK clock LOW time
TCK clock LOW to TDO valid
TCK clock LOW to TDO invalid
TMS set-up to TCK clock rise
TDI set-up to TCK clock rise
Capture set-up to TCK rise
TMS hold after TCK clock rise
TDI hold after clock rise
Capture hold after clock rise
Test Mode Select
Test Data-Out
[10, 11]
Test Data-In
Test Clock
(TDO)
(TMS)
(TCK)
(TDI)
1
Description
t TMSS
t TDIS
2
t TMSH
t TDIH
t TH
DON’T CARE
R
/t
F
t
TL
= 1 ns.
3
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
t CYC
UNDEFINED
4
t TDOX
t TDOV
5
CY7C1355C, CY7C1357C
Min
50
20
20
–
–
0
5
5
5
5
5
5
6
Max
20
10
–
–
–
–
–
–
–
–
–
–
Page 15 of 32
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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