CY7C1357C-100AXCT Cypress Semiconductor Corp, CY7C1357C-100AXCT Datasheet - Page 16

• Manufacturer Part Number: CY7C1357C-100AXCT
• Description: CY7C1357C-100AXCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1357C-100AXCT

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (512K x 18)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.3 V TAP AC Test Conditions
Input pulse levels................................................V
Input rise and fall times....................................................1 ns
Input timing reference levels.......................................... 1.5 V
Output reference levels ................................................. 1.5 V
Test load termination supply voltage ............................. 1.5 V
3.3 V TAP AC Output Load Equivalent
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < T
Identification Register Definitions
Document Number: 38-05539 Rev. *H
V
V
V
V
V
V
I
Revision number (31:29)
Device depth (28:24)
Device width (23:18)
Cypress device ID (17:12)
Cypress JEDEC ID code (11:1)
ID register presence indicator (0)
Note
X
12. All voltages referenced to V
OH1
OH2
OL1
OL2
IH
IL
Parameter
TDO
A
Instruction Field
< +70 °C; V
Z = 50Ω
O
Output HIGH voltage
Output HIGH voltage
Output LOW voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Input load current
DD
SS
= 3.3 V ± 0.165 V unless otherwise noted)
Description
(GND).
1.5V
20pF
00000110100
50Ω
CY7C1355C
(256 K × 36)
I
I
I
I
I
I
GND < V
001001
100110
OH
OH
OH
OL
OL
OL
01010
010
1
= 8.0 mA
= 8.0 mA
= 100 µA
= –4.0 mA, V
= –1.0 mA, V
= –100 µA
SS
to 3.3 V
IN
< V
DDQ
Conditions
00000110100
CY7C1357C
(512 K × 18)
DDQ
DDQ
001001
010110
01010
010
= 3.3 V
= 2.5 V
1
[12]
2.5 V TAP AC Test Conditions
Input pulse levels................................................ V
Input rise and fall time .....................................................1 ns
Input timing reference levels........................................ 1.25 V
Output reference levels ............................................... 1.25 V
Test load termination supply voltage ........................... 1.25 V
2.5 V TAP AC Output Load Equivalent
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
= 3.3 V
= 2.5 V
= 3.3 V
= 2.5 V
= 3.3 V
= 2.5 V
= 3.3 V
= 2.5 V
= 3.3 V
= 2.5 V
TDO
Describes the version number
Reserved for Internal Use
Defines memory type and architecture
Defines width and density
Allows unique identification of SRAM vendor
Indicates the presence of an ID register
Z = 50Ω
CY7C1355C, CY7C1357C
O
–0.5
–0.3
Min
2.4
2.0
2.9
2.1
2.0
1.7
–5
–
–
–
–
Description
V
V
1.25V
DD
DD
Max
0.4
0.4
0.2
0.2
0.7
0.7
–
–
–
–
5
+ 0.3
+ 0.3
20pF
50Ω
Page 16 of 32
SS
Unit
µA
to 2.5 V
V
V
V
V
V
V
V
V
V
V
V
V
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