CY7C199D-10ZXIT Cypress Semiconductor Corp, CY7C199D-10ZXIT Datasheet - Page 6

• Manufacturer Part Number: CY7C199D-10ZXIT
• Description: CY7C199D-10ZXIT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C199D-10ZXIT

• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Memory Size: 256K (32K x 8)
• Speed: 10ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TSOP I
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2014-2

Switching Characteristics
(Over the operating range)
Document Number: 38-05471 Rev. *H
Notes
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
4. Test conditions assume signal transition time of 3 ns or less for all speeds, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the
5. t
6. At any given temperature and voltage condition, t
7. t
8. This parameter is guaranteed by design and is not tested.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write
10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
power
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
specified I
by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
[8]
[8]
POWER
HZOE
[6]
[6]
[6, 7]
[6, 7]
[6, 7]
[5]
[6]
, t
HZCE
Parameter
gives the minimum amount of time that the power supply should be at typical V
OL
, and t
[9, 10]
/I
OH
and 30-pF load capacitance.
HZWE
are specified with C
[4]
V
Read cycle time
Address to data valid
Data hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to low Z
OE HIGH to high Z
CE LOW to low Z
CE HIGH to high Z
CE LOW to power-up
CE HIGH to power-down
Write cycle time
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
Data setup to write end
Data hold from write end
WE LOW to high Z
WE HIGH to low Z
CC(typical)
L
= 5 pF as in part (b) of
to the first access
HZCE
is less than t
Description
“AC Test Loads and Waveforms [3]”
LZCE
, t
HZOE
is less than t
CC
LZOE
HZWE
values until the first memory access can be performed.
, and t
and t
on page 5. Transition is measured 200 mV from steady-state voltage.
HZWE
SD
.
is less than t
Min
100
10
10
–
3
–
–
0
–
3
–
0
–
7
7
0
0
7
6
0
–
3
LZWE
CY7C199D-10
for any given device.
Max
10
10
10
–
–
–
5
–
5
–
5
–
–
–
–
–
–
–
–
–
5
–
CY7C199D
Page 6 of 15
Unit
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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