DSPIC33EP512MU810T-I/PT Microchip Technology, DSPIC33EP512MU810T-I/PT Datasheet - Page 349

• Manufacturer Part Number: DSPIC33EP512MU810T-I/PT
• Description: 100 PINS, 512KB Flash, 52KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP512MU810T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 512KB (170K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 24K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 21-26: CiTRmnCON: ECAN™ TX/RX BUFFER m CONTROL REGISTER
 2009-2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
Note 1:
Note:
TXENm
TXENn
R/W-0
R/W-0
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
This bit is cleared when TXREQ is set.
The buffers, SID, EID, DLC, Data Field and Receive Status registers are located in DMA RAM.
See definition for bits 7-0, controls Buffer n
TXENm: TX/RX Buffer Selection bit
1 = Buffer TRBn is a transmit buffer
0 = Buffer TRBn is a receive buffer
TXABTm: Message Aborted bit
1 = Message was aborted
0 = Message completed transmission successfully
TXLARBm: Message Lost Arbitration bit
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
TXERRm: Error Detected During Transmission bit
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
TXREQm: Message Send Request bit
1 = Requests that a message be sent. The bit automatically clears when the message is successfully
0 = Clearing the bit to ‘0’ while set requests a message abort
RTRENm: Auto-Remote Transmit Enable bit
1 = When a remote transmit is received, TXREQ will be set
0 = When a remote transmit is received, TXREQ will be unaffected
TXmPRI<1:0>: Message Transmission Priority bits
11 = Highest message priority
10 = High intermediate message priority
01 = Low intermediate message priority
00 = Lowest message priority
TXABTm
TXABTn
sent
R-0
R-0
(m = 0,2,4,6; n = 1,3,5,7)
(1)
W = Writable bit
TXLARBm
C = Writable bit, but only ‘0’ can be written to clear the bit
‘1’ = Bit is set
TXLARBn
R-0
R-0
(1)
TXERRm
TXERRn
(1)
R-0
R-0
Preliminary
(1)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TXREQm
TXREQn
R/W-0
R/W-0
(1)
RTRENm
RTRENn
R/W-0
R/W-0
x = Bit is unknown
R/W-0
R/W-0
TXmPRI<1:0>
TXnPRI<1:0>
DS70616E-page 349
R/W-0
R/W-0
bit 8
bit 0