DSPIC33EP512MU810T-I/PT Microchip Technology, DSPIC33EP512MU810T-I/PT Datasheet - Page 437

• Manufacturer Part Number: DSPIC33EP512MU810T-I/PT
• Description: 100 PINS, 512KB Flash, 52KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP512MU810T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 512KB (170K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 24K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

29.0
dsPIC33EPXXXMU806/810/814
PIC24EPXXXGU810/814 devices include several
features intended to maximize application flexibility and
reliability, and minimize cost through elimination of
external components. These are:
• Flexible configuration
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit emulation
TABLE 29-1:
 2009-2011 Microchip Technology Inc.
0xF80000 Reserved
0xF80002 Reserved
0xF80004 FGS
0xF80006 FOSCSEL
0xF80008 FOSC
0xF8000A FWDT
0xF8000C FPOR
0xF8000E FICD
0xF80010 FAS
0xF80012 FUID0
Legend: — = unimplemented bit, read as ‘0’
Note 1:
Address
Note:
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
2:
3:
SPECIAL FEATURES
This data sheet summarizes the features of
the
PIC24EPXXXGU810/814
devices. It is not intended to be a
comprehensive
complement the information in this data
sheet, refer to the related section of the
“dsPIC33E/PIC24E
Manual”, which is available from the
Microchip web site (www.microchip.com).
These bits are reserved for use by development tools and must be programmed as ‘1’.
These bits are reserved on dsPIC33EP256MU806 (64-pin) devices and always read as ‘1’.
BOR should always be enabled for proper operation (BOREN = 1).
Name
dsPIC33EPXXXMU806/810/814
DEVICE CONFIGURATION REGISTER MAP
FWDTEN
IESO
reference
Bit 7
FCKSM<1:0>
—
—
—
—
—
Reserved
Family
WINDIS
families
(1)
Bit 6
source.
—
—
—
—
—
—
Reference
ALTI2C2
IOL1WAY
and
PLLKEN
JTAGEN
and
Preliminary
To
of
Bit 5
—
—
—
GSSK<1:0>
APLK<1:0>
(2)
Reserved
User Unit ID Byte 0
WDTPRE
29.1
The
PIC24EPXXXGU810/814 devices provide nonvolatile
memory implementation for device Configuration bits.
Refer to Section 30. “Device Configuration”
(DS70618)
Reference Manual” for more information on this
implementation.
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select
various device configurations. These bits are mapped
starting at program memory location 0xF80000.
The individual Configuration bit descriptions for the
Configuration registers are shown in
Note that address 0xF80000 is beyond the user program
memory space. It belongs to the configuration memory
space (0x800000-0xFFFFFF), which can only be
accessed using table reads and table writes.
To prevent inadvertent configuration changes during
code execution, some programmable Configuration
bits are write-once. For such bits, changing a device
configuration requires that the device be Reset. For
other Configuration bits, the device configuration
changes immediately after an RTSP operation. The
RTSP Effect column in
device configuration changes after a bit is modified
using RTSP.
The Device Configuration register map is shown in
Table
ALTI2C1
Bit 4
—
—
—
—
29-1.
(1)
Configuration Bits
dsPIC33EPXXXMU806/810/814
BOREN
of
Bit 3
—
—
—
—
—
—
—
the
(3)
Table 29-2
OSCIOFNC POSCMD<1:0>
WDTPOST<3:0>
“dsPIC33E/PIC24E
RSTPRI
Bit 2
—
—
—
—
FNOSC<2:0>
FPWRT<2:0>
indicates when the
DS70616E-page 437
Table
Bit 1
GSS
APL
—
—
ICS<1:0>
29-2.
GWRP
AWRP
Family
Bit 0
—
—
and