AD9865BCPRL Analog Devices Inc, AD9865BCPRL Datasheet - Page 37

• Manufacturer Part Number: AD9865BCPRL
• Description: IC FRONT-END MIXED-SGNL 64-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9865BCPRL

• Rohs Status: RoHS non-compliant
• Rf Type: HPNA, VDSL
• Features: 10-bit ADC(s), 10-bit DAC(s)
• Package / Case: 64-VFQFN, CSP Exposed Pad

CLOCK SYNTHESIZER
The AD9865 generates all its internal sampling clocks, as well as
two user-programmable clock outputs appearing at CLKOUT1
and CLKOUT2, from a single reference source as shown in
Figure 76. The reference source can be either a fundamental
frequency or an overtone quartz crystal connected between
OSCIN and XTAL with the parallel resonant load components
as specified by the crystal manufacturer. It can also be a TTL-
level clock applied to OSCIN with XTAL left unconnected.
The data rate, f
equal. Therefore, the ADC’s sample rate, f
f
f
rate refers to the word rate and should not be confused with the
nibble rate in full-duplex interface.
C1
The 2
filter) and VCO capable of generating an output frequency that
is a multiple of 1, 2, 4, or 8 of its input reference frequency,
f
is between 20 MHz and 80 MHz, while the VCO can operate
over a 40 MHz to 200 MHz span. For the best phase noise/jitter
characteristics, it is advisable to operate the VCO with a fre-
quency between 100 MHz and 200 MHz. The VCO output
drives the TxDAC directly such that its update rate, f
related to f
where M = 0, 1, 2, or 3.
M is the PLL’s multiplication factor set in Register 0x04. The
value of M is determined by the Tx path’s word rate, f
digital interpolation factor, F, as shown in the following
equation:
Note: if the reference frequency appearing at OSCIN is chosen
to be equal to the AD9865’s Tx and Rx path’s word rate, then M
is simply equal to log
The clock source for the ADC can be selected in Register 0x04
as a buffered version of the reference frequency appearing at
OSCIN (default setting) or a divided version of the VCO output
DATA
DATA
OSCIN
XTAL
, depending on the interpolation factor selected. The data
C2
f
M = log
while the TxDAC update rate is a factor of 1, 2, or 4 of
, appearing at OSCIN. The input frequency range of f
DAC
M
CLK multiplier contains a PLL (with integrated loop
= 2
OSCIN
CLKOUT1
M
CLKOUT2
XTAL
OSCIN
2
× f
(F × f
Figure 76. Clock Oscillator and Synthesizer
DATA
by the following equation:
OSCIN
, for the Tx and Rx data paths must always be
DATA
2
(F).
/f
OSCIN
÷ 2
÷ 2
L
R
)
MULTIPLIER
2
M
CLK
ADC
, is always equal to
÷2
N
DAC
DATA
, is
TO ADC
, and
TO TxDAC
OSCIN
(10)
(11)
Rev. A | Page 37 of 48
(f
if f
typically results in the best jitter/phase noise performance for
the ADC sampling clock. The second option is suitable in cases
where f
the divider ratio, N, is chosen such that the divided down VCO
output is equal to the ADC sample rate, as shown in the
following equation:
where N = 0, 1, or 2.
Figure 77 shows the degradation in phase noise performance
imparted onto the ADC’s sampling clock for different VCO
output frequencies. In this case, a 25 MHz, 1 V p-p sine wave
was used to drive OSCIN, and the PLL’s M and N factors were
selected to provide an f
frequencies of 50, 100, and 200 MHz. The RxPGA input was
driven with a near full-scale, 12.5 MHz input signal with a gain
setting of 0 dB. Operating the VCO at the highest possible
frequency results in the best narrow and wideband phase noise
characteristics. For comparison purposes, the clock source for
the ADC was taken directly from OSCIN when driven by a
50 MHz square wave.
The CLK synthesizer also has two clock outputs appearing at
CLKOUT1 and CLKOUT2. They are programmable via
Register 0x06. Both outputs can be inverted or disabled. The
voltage levels appearing at these outputs are relative to DRVDD
and remain active during a hardware or software reset. Table 22
shows the SPI registers pertaining to the clock synthesizer.
CLKOUT1 is a divided version of the VCO output and can be
set to be a submultiple integer of f
or 3). Because this clock is actually derived from the same set of
dividers used within the PLL core, it is phase-locked to them
such that its phase relationship relative to the signal appearing
Figure 77. Comparison of Phase Noise Performance when ADC Clock Source
DAC
–100
–110
OSCIN
–10
–20
–30
–40
–50
–60
–70
–80
–90
). The first option is the default setting and most desirable
0
f
2.5
ADC
OSCIN
is equal to the ADC sample rate, f
= f
4.5
is Derived from Different VCO Output Frequencies
DAC
is a factor of 2 or 4 less than the f
/
6.5
2
N
8.5
FREQUENCY (MHz)
ADC
10.5 12.5
of 50 MHz for VCO operating
14.5
DAC
(f
16.5 18.5
DAC
ADC
DIRECT
VCO = 50MHz
VCO = 100MHz
VCO = 200MHz
/2
R
. This option
ADC
, where R = 0, 1, 2,
20.5
. In this case,
22.5
AD9865
(12)