AD9865BCPRL Analog Devices Inc, AD9865BCPRL Datasheet - Page 38

• Manufacturer Part Number: AD9865BCPRL
• Description: IC FRONT-END MIXED-SGNL 64-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9865BCPRL

• Rohs Status: RoHS non-compliant
• Rf Type: HPNA, VDSL
• Features: 10-bit ADC(s), 10-bit DAC(s)
• Package / Case: 64-VFQFN, CSP Exposed Pad

AD9865
at OSCIN (or RXCLK) can be determined upon power up. Also,
this clock has near 50% duty cycle, because it is derived from
the VCO. As a result, CLKOUT1 should be selected before
CLKOUT2 as the primary source for system clock distribution.
CLKOUT2 is a divided version of the reference frequency, f
and can be set to be a submultiple integer of f
where L = 0, 1, or 2). With L set to 0, the output of CLKOUT2 is
a delayed version of the signal appearing at OSCIN, exhibiting
the same duty cycle characteristics. With L set to 1 or 2, the
output of CLKOUT2 is a divided version of the OSCIN signal,
exhibiting a near 50% duty cycle, but without having a determi-
nistic phase relationship relative to CLKOUT1 (or RXCLK).
OSCIN
(f
OSCIN
/2
L
,
OSCIN
Rev. A | Page 38 of 48
,
Table 22. SPI Registers for CLK Synthesizer
Address (Hex)
0x04
0x06
Bit
(4)
(3:2)
(1:0)
(7:6)
(5)
(4)
(3:2)
(1)
(0)
Description
ADC CLK from PLL
PLL divide factor (P)
PLL multiplication factor (M)
CLKOUT2 divide number
CLKOUT2 invert
CLKOUT2 disable
CLKOUT1 divide number
CLKOUT1 invert
CLKOUT1 disable