CY2SSTV857ZXC-27 Silicon Laboratories Inc, CY2SSTV857ZXC-27 Datasheet - Page 6

• Manufacturer Part Number: CY2SSTV857ZXC-27
• Description: Clock Buffer 2.5V 60-200MHz 1:10 Diff DDR266/333 B/D
• Manufacturer: Silicon Laboratories Inc

Specifications of CY2SSTV857ZXC-27

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.0, November 21, 2006
Absolute Maximum Conditions
Input Voltage Relative to V
Input Voltage Relative to V
Storage Temperature: ................................ –65° C to + 150° C
Operating Temperature:.................................... 0° C to +85° C
Maximum Power Supply: ................................................ 3.5V
DC Electrical Specifications
AC Electrical Specifications
V
V
V
V
V
I
I
I
V
V
V
V
I
I
I
I
Cin
f
t
t
D
Notes:
10. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30kHz and 50 kHz with a down
11. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = t
IN
OL
OH
OZ
DDQ
DD
DDS
CLK
DC
LOCK
tsl(o)
Parameter
2. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Unused inputs must be held HIGH or LOW to prevent them from floating.
4. Differential input signal voltage specifies the differential voltage VTR–VCPI required for switching, where VTR is the true input level and VCP is the complementary
5. Differential cross-point input voltage is expected to track V
6. For load conditions see Figure 6.
7. The value of VOC is expected to be (VTR + VCP)/2. In case of each clock directly terminated by a 120Ω resistor. See Figure 6.
8. All outputs switching load with 14 pF in 60Ω environment. See Figure 6.
9. Parameters are guaranteed by design and characterization. Not 100% tested in production.
Parameter
DDQ
IL
IH
ID
IX
OL
OH
OUT
OC
TYC
input level. See Figure 6.
spread or –0.5%.
where the cycle time(tC) decreases as the frequency goes up.
Supply Voltage
Input Low Voltage
Input High Voltage
Differential Input Voltage
Differential Input Crossing Voltage
Input Current [CLK, FBIN, PD#]
Output Low Current
Output High Current
Output Low Voltage
Output High Voltage
Output Voltage Swing
Output Crossing Voltage
High-Impedance Output Current
Dynamic Supply Current
PLL Supply Current
Standby Supply Current
Input Pin Capacitance
Operating Clock Frequency
Input Clock Duty Cycle
Maximum PLL lock Time
Duty Cycle
Output Clocks Slew Rate
[11]
Description
SS
DDQ
:............................... V
or AV
Description
[6]
DD
(AV
(AV
[7]
[8]
[4]
: ........... V
[2]
DD
DD
= V
= V
DDQ
[5]
DDQ
DDQ
DDQ
Operating
PD#
CLK, FBIN
CLK, FBIN
V
V
V
V
V
V
All V
V
PD# = 0 and CLK/CLK# < 10
MHz
SS
IN
DDQ
DDQ
DDQ
DDQ
O
DDA
= 2.5v ± 5%, T
= 2.5V±5%, T
and is the voltage at which the differential signal must be crossing.
– 0.3V
+ 0.3V
= GND or V
= 0V or V
DDQ
= 2.375V, I
= 2.375V, V
= 2.375V, V
= 2.375V, I
only
, F
Condition
AV
60 MHz to 100 MHz
101 MHz to 170 MHz
20%–80% of VOD
O
IN
= 170 MHz
DD
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V
range:
V
Unused inputs must always be tied to an appropriate logic
voltage level (either V
O
A
= V
A
OL
SS
, V
OH
= 0° C to +85° C)
= V
OUT
OUT
= 0° C to +85° C)
DDQ
= 12 mA
DDQ
< (V
= –12 mA
DDQ
Condition
= 1.2V
= 1V
in
= 2.5V ± 0.2V
or V
out
) < V
0.7 × V
(V
(V
[9, 10]
[3]
DDQ
DDQ
Min.
2.38
0.36
–10
–28
–10
SS
0.2
1.7
1.1
0.2
DDQ
26
in
/2) –
/2) –
and V
or V
DDQ
.
DDQ
Min.
49.5
CY2SSTV857-27
60
40
49
out
1
V
V
).
should be constrained to the
Typ.
DDQ
DDQ
–32
235
2.5
35
9
/2
/2
Typ.
50
0.3 × V
V
(V
V
(V
DDQ
DDQ
DDQ
DDQ
Page 6 of 8
Max.
2.63
300
100
0.2
0.6
0.2
10
10
12
Max.
50.5
4
200
100
60
51
+ 0.3
– 0.4
2
/2) +
/2) +
DDQ
WHC
MHz
V/ns
Unit
Unit
mA
mA
mA
mA
µA
µA
µA
pF
µs
%
%
%
V
V
V
V
V
V
V
V
V
/t
C
,