LAN91C100FD-SS SMSC, LAN91C100FD-SS Datasheet - Page 26

• Manufacturer Part Number: LAN91C100FD-SS
• Description: Ethernet ICs Non-PCI 10/100 Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN91C100FD-SS

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 7 V
• Supply Voltage (min): 0.3 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: QFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BANK 0
BANK 0
Revision 1.0 (09-22-08)
OFFSET
BYTE
BYTE
OFFSET
BYTE
BYTE
HIGH
HIGH
LOW
LOW
Reserved - Must be 0.
Counts four parameters for MAC statistics. When any counter reaches 15 an interrupt is issued. All
counters are cleared when reading the register and do not wrap around beyond 15.
Each four bit counter is incremented every time the corresponding event, as defined in the EPH STATUS
REGISTER bit description, occurs. Note that the counters can only increment once per enqueued transmit
packet, never faster, limiting the rate of interrupts that can be generated by the counters. For example if a
packet is successfully transmitted after one collision the SINGLE COLLISION COUNT field is incremented
by one. If a packet experiences between 2 to 16 collisions, the MULTIPLE COLLISION COUNT field is
incremented by one. If a packet experiences deferral the NUMBER OF DEFERRED TX field is
incremented by one, even if the packet experienced multiple deferrals during its collision retries.
The COUNTER REGISTER facilitates maintaining statistics in the AUTO RELEASE mode where no
transmit interrupts are generated on successful transmissions.
Reading the register in the transmit service routine will be enough to maintain statistics.
FREE MEMORY AVAILABLE - This register can be read at any time to determine the amount of free
memory. The register defaults to the MEMORY SIZE upon reset or upon the RESET MMU command.
MEMORY SIZE - This register can be read to determine the total memory size.
All memory related information is represented in 256 * M byte units, where the multiplier M is determined
by the MCR upper byte.
These register default to FFh, which should be interpreted as 256.
6
8
0
0
1
1
NUMBER OF EXC. DEFFERED TX
MULTIPLE COLLISION COUNT
COUNTER REGISTER
MEMORY INFORMATION
0
0
1
1
REGISTER
NAME
FREE MEMORY AVAILABLE (IN BYTES * 256 * M)
NAME
MEMORY SIZE (IN BYTES *256 * M)
0
0
1
1
DATASHEET
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0
0
1
1
READ ONLY
TYPE
READ ONLY
0
0
1
1
FEAST Fast Ethernet Controller with Full Duplex Capability
NUMBER OF DEFFERED TX
SINGLE COLLISION COUNT
TYPE
0
0
1
1
SYMBOL
0
0
1
1
SMSC LAN91C100FD Rev. D
ECR
SYMBOL
MIR
0
0
1
1