LAN91C100FD-SS SMSC, LAN91C100FD-SS Datasheet - Page 55

• Manufacturer Part Number: LAN91C100FD-SS
• Description: Ethernet ICs Non-PCI 10/100 Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN91C100FD-SS

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 7 V
• Supply Voltage (min): 0.3 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: QFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 7
7.1
7.2
SMSC LAN91C100FD Rev. D
FEAST Fast Ethernet Controller with Full Duplex Capability
nBE0 nBE1
nBE2 nBE3
nRDYRTN
nRESET
VL BUS
SIGNAL
A2-A15
nLRDY
The LAN91C100FD is envisioned to fit a few different bus types. This section describes the basic
guidelines, system level implications and sample configurations for the most relevant bus types. All
applications are based on buffered architectures with a private SRAM bus.
Fast Ethernet Slave Adapter
Slave non-intelligent board implementing 100 Mbps and 10 Mbps speeds.
Adapter requires:
a)
b)
c)
d)
e)
f)
Target systems:
a)
b)
c)
VL Local Bus 32 Bit Systems
On VL Local Bus and other 32 bit embedded systems the LAN91C100FD is accessed as a 32 bit
peripheral in terms of the bus interface. All registers except the DATA REGISTER will be accessed using
byte or word instructions. Accesses to the DATA REGISTER could use byte, word, or dword instructions.
M/nIO
W/nR
LCLK
LAN91C100FD chip
Four SRAMs (32k x 8 - 25ns)
Serial EEPROM (93C46)
Mbps ENDEC and transceiver chip
Mbps MII compliant PHY
Some bus specific glue logic
VL Local Bus 32 bit systems
High-end ISA or non-burst EISA machines
EISA 32 bit slave
LAN91C100
nSRDY and
nBE0 nBE1
nBE2 nBE3
Application Considerations
some logic
nRDYRTN
SIGNAL
A2-A15
RESET
W/nR
LCLK
AEN
Table 7.1 - VL Local Bus Signal Connections
Address bus used for I/O space and register decoding, latched
by nADS rising edge, and transparent on nADS low time.
Qualifies valid I/O decoding - enabled access when low. This
signal is latched by nADS rising edge and transparent on nADS
low time.
Direction of access. Sampled by the LAN91C100FD on first
rising clock that has nCYCLE active. High on writes, low on
reads.
Ready return. Direct connection to VL bus.
nSRDY has the appropriate functionality and timing to create the
VL nLRDY except that nLRDY behaves like an open drain output
most of the time.
Local Bus Clock. Rising edges used for synchronous bus
interface transactions.
Connected via inverter to the LAN91C100FD.
Byte enables. Latched transparently by nADS rising edge.
DATASHEET
Page 55
NOTES
Revision 1.0 (09-22-08)