MT48LC4M16A2TG-75 IT:G TR Micron Technology Inc, MT48LC4M16A2TG-75 IT:G TR Datasheet - Page 30

• Manufacturer Part Number: MT48LC4M16A2TG-75 IT:G TR
• Description: DRAM Chip SDRAM 64M-Bit 4Mx16 3.3V 54-Pin TSOP-II T/R
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC4M16A2TG-75 IT:G TR

• Package: 54TSOP-II
• Density: 64 Mb
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Clock Rate: 133 MHz
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: -40 to 85 °C
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 54-TSOP II
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1090-2

Figure 18:
Figure 19:
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
WRITE Command
WRITE Burst
Note:
An example is shown in Figure 20 on page 31. Data n + 1 is either the last of a burst of two
or the last desired of a longer burst. The 64Mb SDRAM uses a pipelined architecture and
therefore does not require the 2n rule associated with a prefetch architecture. A WRITE
command can be initiated on any clock cycle following a previous WRITE command.
Full-speed random write accesses within a page can be performed to the same bank, as
shown in Figure 21 on page 32, or each subsequent WRITE may be performed to a
different bank.
A8, A9, A11: x16
COMMAND
ADDRESS
A9, A11: x8
A0–A9: x4
A0–A8: x8
A0–A7: x16
NOTE: BL = 2. DQM is LOW.
BA0, BA1
CLK
A11: x4
DQ
RAS#
CAS#
WE#
CKE
A10
CLK
CS#
WRITE
BANK,
COL n
TRANSITIONING DATA
T0
D
n
IN
HIGH
VALID ADDRESS
NOP
n + 1
T1
D
IN
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
NOP
T2
ADDRESS
COLUMN
ADDRESS
30
BANK
DON’T CARE
T3
NOP
DON’T CARE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64Mb: x4, x8, x16 SDRAM
©2000 Micron Technology, Inc. All rights reserved.
Commands