MT48LC4M32LFF5-8 IT:G TR Micron Technology Inc, MT48LC4M32LFF5-8 IT:G TR Datasheet - Page 42

• Manufacturer Part Number: MT48LC4M32LFF5-8 IT:G TR
• Description: DRAM Chip Mobile SDRAM 128M-Bit 4Mx32 3.3V 90-Pin VFBGA T/R
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48LC4M32LFF5-8 IT:G TR

• Density: 128 Mb
• Maximum Clock Rate: 125 MHz
• Package: 90VFBGA
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 19|8|7 ns
• Operating Temperature: -40 to 85 °C
• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 128M (4Mx32)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 90-VFBGA
• Organization: 4Mx32
• Address Bus: 14b
• Access Time (max): 19/8/7ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 115mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 31:
Figure 32:
WRITE with Auto Precharge
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
READ With Auto Precharge Interrupted by a READ
READ With Auto Precharge Interrupted by a WRITE
Internal
States
Internal
States
Notes:
Notes:
COMMAND
COMMAND
ADDRESS
ADDRESS
BANK m
BANK m
1. DQM is LOW, BL = 4 or greater, and CL = 3.
1. DQM is HIGH at T2 to prevent D
• Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
BANK n
BANK n
DQM
rupt a WRITE on bank n when registered, with the data-out appearing CL later. The
precharge to bank n will begin after
bank m is registered. The last valid WRITE to bank n will be data-in registered 1 clock
prior to the READ to bank m (Figure 33 on page 43).
CLK
CLK
DQ
DQ
1
Active
Page
READ - AP
BANK n,
Page Active
BANK n
COL a
T0
T0
NOP
READ with Burst of 4
CAS Latency = 3 (BANK n)
READ - AP
BANK n,
Page Active
Page Active
BANK n
COL a
T1
T1
NOP
READ with Burst of 4
CL = 3 (BANK n)
T2
T2
NOP
NOP
42
READ - AP
BANK m,
T3
BANK m
T3
COL d
OUT
D
NOP
OUT
a
Interrupt Burst, Precharge
READ with Burst of 4
a + 1 from contending with D
TRANSITIONING DATA
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
WR is met, where
TRANSITIONING DATA
BANK m,
WRITE - AP
COL d
BANK m
T4
T4
CL = 3 (BANK m)
D
NOP
d
IN
Interrupt Burst, Precharge
D
WRITE with Burst of 4
OUT
a
t
RP - BANK n
128Mb: x16, x32 Mobile SDRAM
T5
T5
d + 1
NOP
NOP
D
IN
D
a + 1
OUT
t
RP - BANK n
T6
T6
NOP
NOP
d + 2
t
D
WR begins when the READ to
IN
D
OUT
d
DON’T CARE
DON’T CARE
©2001 Micron Technology, Inc. All rights reserved.
Idle
IN
T7
T7
t WR - BANK m
NOP
NOP
d + 3
D
t RP - BANK m
IN
Precharge
Write-Back
D
d + 1
d at T4.
OUT
Idle
READs