MT48LC8M16A2TG-75:G Micron Technology Inc, MT48LC8M16A2TG-75:G Datasheet - Page 38

• Manufacturer Part Number: MT48LC8M16A2TG-75:G
• Description: DRAM Chip SDRAM 128M-Bit 8Mx16 3.3V 54-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC8M16A2TG-75:G

• Density: 128 Mb
• Maximum Clock Rate: 133 MHz
• Package: 54TSOP-II
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: 0 to 70 °C
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 54-TSOP II
• Organization: 8Mx16
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 150mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant

Figure 29:
BURST READ/SINGLE WRITE
Concurrent Auto Precharge
READ with Auto Precharge
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
Clock Suspend During READ Burst
Notes:
COMMAND
1. For this example, CL = 2, BL = 4 or greater, and DQM is LOW.
The burst read/single write mode is entered by programming the write burst mode bit
(M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the
access of a single column location (burst of one), regardless of the programmed BL.
READ commands access columns according to the programmed BL and sequence, just
as in the normal mode of operation (M9 = 0).
An access command (READ or WRITE) to another bank while an access command with
auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM
supports concurrent auto precharge. Micron SDRAMs support concurrent auto
precharge. Four cases where concurrent auto precharge occurs are defined below.
• Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
INTERNAL
ADDRESS
rupt a READ on bank n, CL later. The precharge to bank n will begin when the READ
to bank m is registered (Figure 30 on page 39).
interrupt a READ on bank n when registered. DQM should be used 2 clocks prior to
the WRITE command to prevent bus contention. The precharge to bank n will begin
when the WRITE to bank m is registered (Figure 31 on page 39).
CLOCK
CKE
CLK
DQ
T0
BANK,
COL n
READ
T1
NOP
38
T2
NOP
D
OUT
n
TRANSITIONING DATA
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
n + 1
D
OUT
T4
NOP
128Mb: x4, x8, x16 SDRAM
T5
NOP
n + 2
D
OUT
©1999 Micron Technology, Inc. All rights reserved.
DON’T CARE
T6
NOP
D
n + 3
OUT
Operations