N25Q128A13BSF40G NUMONYX, N25Q128A13BSF40G Datasheet - Page 128
N25Q128A13BSF40G
Manufacturer Part Number
N25Q128A13BSF40G
Description
SERIAL NOR
Manufacturer
NUMONYX
Datasheet
1.N25Q128A13BSF40G.pdf
(180 pages)
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9.2.23
9.2.24
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Read Volatile Enhanced Configuration Register
The Read Volatile Enhanced Configuration Register (RDVECR) instruction allows the
Volatile Configuration Register to be read.
Figure 66. Read Volatile Enhanced Configuration Register instruction sequence
Write Volatile Enhanced Configuration Register
The Write Volatile Enhanced Configuration register (WRVECR) instruction allows new
values to be written to the Volatile Enhanced Configuration register. Before it can be
accepted, a write enable (WREN) instruction must previously have been executed. In case
of Fast POR, the WREN instruction is not required because a WREN instruction gets the
device out from the Fast POR state (See
Apart form the parallelizing of the instruction code and the input data on the two pins DQ0
and DQ1, the instruction functionality is exactly the same as the Write Volatile Enhanced
Configuration Register (WRVECR) instruction of the Extended SPI protocol, please refer to
Section 9.1.33: Write Volatile Enhanced Configuration Register
DQ0
DQ1
C
S
DIO-SPI
0
Instruction
1
2
3
7
6
4
Configuration Register Out
Section 11.1: Fast
5
4
5
Byte
Volatile Enhanced
3
2
6
1
0
7
7
6
8
5
4
9 10 11
POR).
Byte
Dual_Read_VECR
3
2
for further details.
1
0
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