N25Q128A13BSF40G NUMONYX, N25Q128A13BSF40G Datasheet - Page 158

• Manufacturer Part Number: N25Q128A13BSF40G
• Description: SERIAL NOR
• Manufacturer: NUMONYX

Table 24.
Note:
158/180
(WRNVCR
opcode)
B1h
DQ0
DQ1
DQ3
DQ2
Vd
S
NVCR check: XIP enabled
6 dummy cycles
NVCR XIP bits setting example
Figure 97. XIP mode directly after power on
Xb is the XIP Confirmation bit, and it should be set to '0' to keep XIP state or '1' to exit XIP
mode and return to standard read mode.
for fast read
instructions
t
VSI
+ 0110
(<100μ)
C
default; Quad
Mode 3
Mode 0
XIP set as
I/O mode
100
A23-16 A15-8 A7-0
0
4
5
6
7
1
0
1
2
3
driver strength
Output Buffer
2
4
5
6
7
default
3
111
0
1
2
3
4
4
5
6
7
5
0
1
2
3
6
Xb
Dummy (ex.: 6)
FAST POR
7
enabled
8
0
9 10 11 12 13 14
not disabled
Hold/Reset
Byte 1
6
5
7
4
IO switches from Input to Output
3
Quad_XIP_After_Power-On
0
1
2
1
Byte 2
6
7
4
5
15 16
2
3
0
1
SPI protocol
6
7
4
5
Extended
11
Don’t
Care
xx