M4-128N/64-15JC LATTICE SEMICONDUCTOR, M4-128N/64-15JC Datasheet - Page 16

• Manufacturer Part Number: M4-128N/64-15JC
• Description: CPLD MACH 4 Family 5K Gates 128 Macro Cells 41.7MHz/55.6MHz EECMOS Technology 5V 84-Pin PLCC Tube
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of M4-128N/64-15JC

• Package: 84PLCC
• Family Name: MACH 4
• Device System Gates: 5000
• Number Of Macro Cells: 128
• Maximum Propagation Delay Time: 15 ns
• Number Of User I/os: 64
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 41.7|55.6 MHz
• Number Of Product Terms Per Macro: 20
• Re-programmability Support: Yes
• Operating Temperature: 0 to 70 °C

Macrocell
The macrocell consists of a storage element, routing resources, a clock multiplexer, and
initialization control. The macrocell has two fundamental modes: synchronous and
asynchronous (Figure 5). The mode chosen only affects clocking and initialization in the
macrocell.
In either mode, a combinatorial path can be used. For combinatorial logic, the synchronous
mode will generally be used, since it provides more product terms in the allocator.
10
From Logic Allocator
From PAL-Block
Clock Generator
Individual Clock
Product Term
Product Term
Product Terms
Initialization
From Logic
Initialization
Individual
Allocator
PAL-Clock
Individual macrocell resources
PAL-Block
Generator
Common PAL-block resource
From
Power-Up
Block CLK0
Block CLK1
Reset
Block CLK0
Block CLK1
Block CLK2
Block CLK3
Power-Up
Reset
a. Synchronous mode
b. Asynchronous mode
Figure 5. Macrocell
MACH 4 Family
SWAP
D/T/L
AP
D/T/L
AP
AR
Q
AR
Q
To Output and Input
Switch Matrices
To Output and Input
Switch Matrices
17466G-009
17466G-010