M4-128N/64-15JC LATTICE SEMICONDUCTOR, M4-128N/64-15JC Datasheet - Page 22

• Manufacturer Part Number: M4-128N/64-15JC
• Description: CPLD MACH 4 Family 5K Gates 128 Macro Cells 41.7MHz/55.6MHz EECMOS Technology 5V 84-Pin PLCC Tube
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of M4-128N/64-15JC

• Package: 84PLCC
• Family Name: MACH 4
• Device System Gates: 5000
• Number Of Macro Cells: 128
• Maximum Propagation Delay Time: 15 ns
• Number Of User I/os: 64
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 41.7|55.6 MHz
• Number Of Product Terms Per Macro: 20
• Re-programmability Support: Yes
• Operating Temperature: 0 to 70 °C

I/O Cell
The I/O cell (Figures 10 and 11) simply consists of a programmable output enable, a feedback
path, and flip-flop (except MACH 4 devices with 1:1 macrocell-I/O cell ratio.) An individual
output enable product term is provided for each I/O cell. The feedback signal drives the input
switch matrix.
The I/O cell (Figure 10) contains a flip-flop, which provides the capability for storing the input
in a D-type register or latch. The clock can be any of the PAL block clocks. Both the direct and
registered versions of the input are sent to the input switch matrix. This allows for such functions
as “time-domain-multiplexed” data comparison, where the first data value is stored, and then the
second data value is put on the I/O pin and compared with the previous stored value.
Note that the flip-flop used in the MACH 4 I/O cell is independent of the flip-flops in the
macrocells. It powers up to a logic low.
Zero-Hold-Time Input Register
The MACH 4 devices have a zero-hold-time (ZHT) fuse which controls the time delay associated
with loading data into all I/O cell registers and latches. When programmed, the ZHT fuse
increases the data path setup delays to input storage elements, matching equivalent delays in
the clock path. When the fuse is erased, the setup time to the input storage element is minimized.
This feature facilitates doing worst-case designs for which data is loaded from sources which
have low (or zero) minimum output propagation delays from clock edges.
Input Switch Matrix
The input switch matrix (Figures 12 and 13) optimizes routing of inputs to the central switch
matrix. Without the input switch matrix, each input and feedback signal has only one way to
enter the central switch matrix. The input switch matrix provides additional ways for these
signals to enter the central switch matrix.
16
Figure 10. I/O Cell for MACH 4 Devices with 2:1
Output Enable
Switch Matrix
Product Term
From Output
Individual
Switch
Matrix
Input
To
Macrocell-I/O Cell Ratio
Q
D/L
Block CLK0
Block CLK1
Block CLK2
Block CLK3
Power-up reset
17466G-017
MACH 4 Family
Figure 11. I/O Cell for MACH 4 Devices with 1:1
Output Enable
Switch Matrix
Product Term
From Output
Individual
Switch
Matrix
Input
To
Macrocell-I/O Cell Ratio
17466G-018