XC2S100E-6FT256I Xilinx Inc, XC2S100E-6FT256I Datasheet - Page 15

• Manufacturer Part Number: XC2S100E-6FT256I
• Description: FPGA Spartan®-IIE Family 100K Gates 2700 Cells 357MHz 0.15um Technology 1.8V 256-Pin FTBGA
• Manufacturer: Xilinx Inc

Specifications of XC2S100E-6FT256I

• Package: 256FTBGA
• Family Name: Spartan®-IIE
• Device Logic Cells: 2700
• Device Logic Units: 600
• Device System Gates: 100000
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 182
• Ram Bits: 40960

Each CLB has four direct feedthrough paths, one per LC.
These paths provide extra data input lines or additional local
routing that does not consume logic resources.
Arithmetic Logic
Dedicated carry logic provides capability for high-speed
arithmetic functions. The Spartan-IIE FPGA CLB supports
two separate carry chains, one per slice. The height of the
carry chains is two bits per CLB.
The arithmetic logic includes an XOR gate that allows a
1-bit full adder to be implemented within an LC. In addition,
a dedicated AND gate improves the efficiency of multiplier
implementations.
The dedicated carry path can also be used to cascade func-
tion generators for implementing wide logic functions.
BUFTs
Each Spartan-IIE FPGA CLB contains two 3-state drivers
(BUFTs) that can drive on-chip busses. The IOBs on the left
and right sides can also drive the on-chip busses. See
icated Routing, page
has an independent 3-state control pin and an independent
input pin. The 3-state control pin is an active-Low enable
(T). When all BUFTs on a net are disabled, the net is High.
There is no need to instantiate a pull-up unless desired for
simulation purposes. Simultaneously driving BUFTs onto
the same net will not cause contention. If driven both High
and Low, the net will be Low.
DS077-2 (v2.3) June 18, 2008
Product Specification
Figure 7: F5 and F6 Multiplexers
R
CLB
Slice
Slice
LUT
LUT
LUT
LUT
17. Each Spartan-IIE FPGA BUFT
MUXF5
MUXF5
DS077-2_05-111501
MUXF6
Ded-
www.xilinx.com
Block RAM
Spartan-IIE FPGAs incorporate several large block RAM
memories. These complement the distributed RAM
Look-Up Tables (LUTs) that provide shallow memory struc-
tures implemented in CLBs.
Block RAM memory blocks are organized in columns. Most
Spartan-IIE devices contain two such columns, one along
each vertical edge. The XC2S400E has four block RAM col-
umns and the XC2S600E has six block RAM columns.
These columns extend the full height of the chip. Each
memory block is four CLBs high, and consequently, a
Spartan-IIE device 16 CLBs high will contain four memory
blocks per column, and a total of eight blocks.
Table 6: Spartan-IIE Block RAM Amounts
Each block RAM cell, as illustrated in
chronous dual-ported 4096-bit RAM with independent con-
trol signals for each port. The data widths of the two ports
can
bus-width conversion.
Spartan-IIE
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
XC2S50E
Device
be
Spartan-IIE FPGA Family: Functional Description
configured
Figure 8: Dual-Port Block RAM
WEA
ENA
RSTA
ADD[#:0]
DIA[#:0]
WEB
ENB
RSTB
ADDRB[#:0]
DIB[#:0]
CLKA
CLKB
# of Blocks
RAMB4_S#_S#
independently,
10
12
14
16
40
72
8
DOA[#:0]
DOB[#:0]
Figure
Total Block RAM
providing
DS001_05_060100
8, is a fully syn-
160K
288K
Bits
32K
40K
48K
56K
64K
built-in
15