XC2S100E-6FT256I Xilinx Inc, XC2S100E-6FT256I Datasheet - Page 29
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XC2S100E-6FT256I
Manufacturer Part Number
XC2S100E-6FT256I
Description
FPGA Spartan®-IIE Family 100K Gates 2700 Cells 357MHz 0.15um Technology 1.8V 256-Pin FTBGA
Manufacturer
Xilinx Inc
Datasheet
1.XC2S50E-6TQG144C.pdf
(108 pages)
Specifications of XC2S100E-6FT256I
Package
256FTBGA
Family Name
Spartan®-IIE
Device Logic Cells
2700
Device Logic Units
600
Device System Gates
100000
Maximum Internal Frequency
357 MHz
Typical Operating Supply Voltage
1.8 V
Maximum Number Of User I/os
182
Ram Bits
40960
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Revision History
DS077-2 (v2.3) June 18, 2008
Product Specification
Version No.
1.0
2.0
2.1
2.3
R
11/15/01
11/18/02
07/09/03
06/18/08
Date
Initial Xilinx release.
Added XC2S400E and XC2S600E. Removed Preliminary designation. Clarified details of I/O
standards, boundary scan, and configuration.
Added hot swap description (see
Table 9
Added note that TDI, TMS, and TCK have a default pull-up resistor. Add note on maximum
daisy-chain limit. Updated
Updated all modules for continuous page, figure, and table numbering. Updated links.
Synchronized all modules to v2.3.
containing JTAG IDCODE values. Clarified configuration PROM support.
www.xilinx.com
Figure 19
Hot Swap, Hot Insertion, Hot Socketing
since Mode pins can be pulled up to either 2.5V or 3.3V.
Description
Spartan-IIE FPGA Family: Functional Description
Support). Added
29
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