XC2S100E-6FT256I Xilinx Inc, XC2S100E-6FT256I Datasheet - Page 20

• Manufacturer Part Number: XC2S100E-6FT256I
• Description: FPGA Spartan®-IIE Family 100K Gates 2700 Cells 357MHz 0.15um Technology 1.8V 256-Pin FTBGA
• Manufacturer: Xilinx Inc

Specifications of XC2S100E-6FT256I

• Package: 256FTBGA
• Family Name: Spartan®-IIE
• Device Logic Cells: 2700
• Device Logic Units: 600
• Device System Gates: 100000
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 182
• Ram Bits: 40960

Spartan-IIE FPGA Family: Functional Description
Bit Sequence
The bit sequence within each IOB is: In, Out, 3-State. The
input-only pins contribute only the In bit to the boundary
scan I/O data register, while the output-only pins contributes
all three bits.
From a cavity-up view of the chip (as shown in the FPGA
Editor), starting in the upper right chip corner, the boundary
scan data-register bits are ordered as shown in
BSDL (Boundary Scan Description Language) files for
Spartan-IIE family devices are available on the Xilinx web
site at:
http://www.xilinx.com/support/download/sp2ebsdl.htm.
Spartan-IIE FPGA boundary scan IDCODE values are
shown in
Table 9: Spartan-IIE IDCODE Values
Development System
Spartan-IIE FPGAs are supported by the Xilinx ISE
tools. The basic methodology for Spartan-IIE FPGA design
consists of three interrelated steps: design entry, imple-
mentation, and verification. Industry-standard tools are
used for design entry and simulation, while Xilinx provides
proprietary architecture-specific tools for implementation.
The Xilinx development system is integrated under the
Xilinx Project Navigator software, providing designers with a
common user interface regardless of their choice of entry
and verification tools. The software simplifies the selection
of implementation options with pull-down menus and on-line
help.
Several advanced software features facilitate Spartan-IIE
FPGA design. CORE Generator™ tool functions, for exam-
ple, include macros with relative location constraints to
guide their placement. They help ensure optimal implemen-
tation of common functions.
20
XC2S50E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
Device
Table
9.
Version
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
0000 101
0000 101
0000 101
0000 101
0000 101
0000 101
0000 101
Family
Figure
®
www.xilinx.com
CAE
15.
0 0001 0000
0 0001 0100
0 0001 1000
0 0001 1100
0 0010 0000
0 0010 1000
0 0011 0000
Array Size
For HDL design entry, the Xilinx FPGA development system
provides interfaces to several synthesis design environ-
ments.
A standard interface-file specification, Electronic Design
Interchange Format (EDIF), simplifies file transfers into and
out of the development system.
Spartan-IIE FPGAs are supported by a unified library of
standard functions. This library contains over 400 primitives
and macros, ranging from 2-input AND gates to 16-bit accu-
mulators, and includes arithmetic functions, comparators,
counters, data registers, decoders, encoders, I/O functions,
latches, Boolean functions, multiplexers, shift registers, and
barrel shifters.
The design environment supports hierarchical design entry,
with high-level designs that comprise major functional
blocks, while lower-level designs define the logic in these
blocks. These hierarchical design elements are automati-
cally combined by the implementation tools. Different
design entry tools can be combined within a hierarchical
IDCODE
Bit 0 ( TDO end)
Bit 1
Bit 2
Figure 15: Boundary Scan Bit Sequence
(TDI end)
0000 1001 001
0000 1001 001
0000 1001 001
0000 1001 001
0000 1001 001
0000 1001 001
0000 1001 001
Manufacturer
TDO.T
TDO.O
Top-edge IOBs (Right to Left)
Left-edge IOBs (Top to Bottom)
MODE.I
Bottom-edge IOBs (Left to Right)
Right-edge IOBs (Bottom to Top)
BSCANT.UPD
DS077-2 (v2.3) June 18, 2008
Product Specification
Required
DS001_10_032300
1
1
1
1
1
1
1
R