854054AGLF IDT, Integrated Device Technology Inc, 854054AGLF Datasheet
854054AGLF
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854054AGLF Summary of contents
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Integrated Circuit Systems, Inc ENERAL ESCRIPTION The ICS854054 is a 4:1 Differential-to-LVDS Clock IC S Multiplexer which can operate up to 2.8GHz and HiPerClockS™ member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. ...
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Integrated Circuit Systems, Inc ABLE IN ESCRIPTIONS ...
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Integrated Circuit Systems, Inc BSOLUTE AXIMUM ATINGS Supply Voltage Inputs, V -0. Outputs Continuous Current 10mA Surge Current 15mA Package Thermal Impedance, JA Storage Temperature, T -65°C to 150°C STG ...
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Integrated Circuit Systems, Inc. T 4D. LVDS DC C ABLE HARACTERISTICS ...
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Integrated Circuit Systems, Inc. The spectral purity in a band at a specific offset from the funda- mental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise ...
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Integrated Circuit Systems, Inc. P ARAMETER 3.3V±5% Power Supply LVDS Float GND + - 3. UTPUT OAD EST IRCUIT nPCLK0:3 PCLK0:3 nQ0 ROPAGATION ELAY 80% Clock 20% Outputs t R ...
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Integrated Circuit Systems, Inc IRING THE IFFERENTIAL NPUT TO Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V generated by the bias resistors R1, R2 ...
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Integrated Circuit Systems, Inc. LVPECL LOCK NPUT NTERFACE The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both V and V SWING and V input requirements. Figures show inter- CMR face examples ...
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Integrated Circuit Systems, Inc. LVDS D T RIVER ERMINATION A general LVDS interface is shown in Figure 100 differential transmission line environment, LVDS drivers re- quire a matched load termination of 100 3.3V LVDS_Driv er 100 Ohm ...
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Integrated Circuit Systems, Inc. This section provides information on power dissipation and junction temperature for the ICS854054. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS854054 is the sum of the core ...
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Integrated Circuit Systems, Inc ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The ...
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Integrated Circuit Systems, Inc ACKAGE UTLINE UFFIX FOR T ABLE Reference Document: JEDEC Publication 95, MO-153 854054AG D IFFERENTIAL TSSOP EAD ACKAGE IMENSIONS ...
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Integrated Circuit Systems, Inc ABLE RDERING NFORMATION ...