DJLXT360LE.A2 Cortina Systems Inc, DJLXT360LE.A2 Datasheet - Page 14

• Manufacturer Part Number: DJLXT360LE.A2
• Manufacturer: Cortina Systems Inc

Specifications of DJLXT360LE.A2

• Number Of Transceivers: 1
• Operating Supply Voltage (typ): 5V
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Supplier Unconfirmed

LXT360 Transceiver
Datasheet: Long Form
249231, Revision 2.1
24 January 2008
2.0
2.1
2.1.1
2.2
2.2.1
Cortina Systems
Functional Description
The LXT360 Transceiver is a fully integrated, PCM transceiver for long- or short-haul, 1.544
Mbps (T1) or 2.048 Mbps (E1) applications allowing full-duplex transmission of digital data
over existing twisted-pair installations. It interfaces with two twisted-pair lines (one pair each
for transmit and receive) through standard pulse transformers and appropriate resistors.
Figure 1 on page 7
configure the device for either Host or Hardware control. In Host mode, control is via the
serial microprocessor port. In Hardware mode, individual pin settings allow stand-alone
operation.
The transceiver provides a high-precision, crystal-less jitter attenuator. The user may place it
in the transmit or receive path, or bypass it completely.
The LXT360 Transceiver meets or exceeds FCC, ANSI T1 and AT&T specifications for CSU
and DSX-1 applications, as well as ITU and ETSI requirements for E1 ISDN PRI
applications.
Initialization
During power up, the transceiver remains static until the power supply reaches
approximately 3 V . Upon crossing this threshold, the device begins a 32 ms reset cycle to
calibrate the Phase Lock Loops (PLL). The transceiver uses a reference clock to calibrate the
PLLs: the transmitter reference is TCLK, and the receiver reference clock is MCLK. MCLK is
mandatory for chip operation and must be an independent free running jitter free reference
clock.
Reset Operation
A reset operation initializes the status and state machines for the LOS, AIS, NLOOP , and
QRSS blocks. In Hardware mode, holding pins RLOOP , LLOOP and TAOS High for at least
one clock cycle resets the device. In Host mode, writing a 1 to the bit CR2.RESET
commands a reset which clears all registers to 0. Allow 32 ms for the device to settle after
removing all reset conditions.
Transmitter
Transmit Digital Data Interface
Input data for transmission onto the line is clocked serially into the device at the TCLK rate.
TPOS and TNEG are the bipolar data inputs. In Unipolar mode, the TDATA pin accepts
unipolar data.
Input data may pass through either the Jitter Attenuator or B8ZS/HDB3 encoder or both. In
Host mode, setting CR1.ENCENB = 1 enables B8ZS/HDB3 encoding. In Hardware mode,
connecting the MODE pin to Midrange selects zero suppression coding. With zero
suppression enabled, the EC1 through EC4 inputs determine the coding scheme as listed in
Table 10 on page
TCLK supplies input synchronization. See the
requirements for TCLK and the Master Clock (MCLK).
®
LXT360 Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
31.
shows a block diagram of the LXT360 Transceiver. The designer can
Figure 16 on page 46
TM
TM
2.0 Functional Description
for the transmit timing
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