DJLXT360LE.A2 Cortina Systems Inc, DJLXT360LE.A2 Datasheet - Page 15

DJLXT360LE.A2

Manufacturer Part Number
DJLXT360LE.A2
Description
Manufacturer
Cortina Systems Inc
Datasheet

Specifications of DJLXT360LE.A2

Number Of Transceivers
1
Operating Supply Voltage (typ)
5V
Screening Level
Industrial
Mounting
Surface Mount
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Supplier Unconfirmed

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DJLXT360LE.A2
Manufacturer:
Intel
Quantity:
10 000
Company:
Part Number:
DJLXT360LE.A2
Quantity:
1 000
LXT360 Transceiver
Datasheet: Long Form
249231, Revision 2.1
24 January 2008
2.2.2
2.2.3
Figure 3
2.2.4
2.2.5
Cortina Systems
Transmit Monitoring
The transmitter includes a short circuit limiter that limits the current sourced into a low
impedance load. The limiter automatically resets when the load current drops below the limit.
The current is determined by the interface circuitry (total resistance on transmit side).
In Host mode, the Performance Status Register flags open circuits in bit PSR.DFMO. A
transition on DFMO will provide an interrupt, and its transition sets bit TSR.DFMO = 1.
Writing a 1 in bit ICR.CDFMO clears the interrupt; leaving a 1 in the bit masks that interrupt.
Transmit Drivers
The transceiver transmits data as a 50% line code as shown in
consumption, the line driver is active only during transmission of marks, and is disabled
during transmission of spaces. Biasing of the transmit DC level is on-chip.
50% Duty Cycle Coding
Transmit Idle Mode
Transmit Idle mode allows multiple transceivers to be connected to a single line for
redundant applications. When TCLK is not present, Transmit Idle mode becomes active, and
TTIP and TRING change to the high impedance state. Remote loopback, Dual loopback,
TAOS, or detection of Network Loop Up code in the receive direction will temporarily disable
the high impedance state.
Transmit Pulse Shape
As shown in
the transmitted pulse shape. In Host mode, EC1 through 4 are established by bits 0 through
3 of Control Register #1 (CR1), respectively. In Hardware mode, pins EC1, EC2, EC3, and
EC4 specify pulse shape.
®
LXT360 Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Table 10 on page
Bit Cell
1
31, Equalizer Control inputs (EC1 through EC4) determine
0
TM
TM
Figure
1
3. To reduce power
2.2 Transmitter
Page 15

Related parts for DJLXT360LE.A2