SLXT332QE.G2 S E001 Intel, SLXT332QE.G2 S E001 Datasheet
SLXT332QE.G2 S E001
Specifications of SLXT332QE.G2 S E001
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SLXT332QE.G2 S E001 Summary of contents
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... Meets or exceeds industry specifications including ITU G.703, ANSI T1.403, AT&T Pub 62411 and ITU-T G.742 Compatible with most industry standard framers As of January 15, 2001, this document replaces the Level One document LXT332 — Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation. Datasheet Computer to PBX interface (CPI & ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. ...
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Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation — LXT332 Contents 1.0 Overview ........................................................................................................................ 6 1.1 Standard LXT332 Features ................................................................................... 6 1.1.1 Tri-state Outputs....................................................................................... 6 1.1.2 Bipolar or Unipolar Data I/O ..................................................................... 6 1.1.3 B8ZS or HDB3 Zero Suppression ...
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LXT332 — Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation 5.0 Test Specifications 6.0 Mechanical Specifications Figures 1 LXT332 Block Diagram ......................................................................................... 5 2 LXT332 Pin Assignments and Package Markings (PLCC) ................................... 8 3 LXT332 Pin Assignments and Package ...
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Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation — LXT332 Figure 1. LXT332 Block Diagram QRSS / BPV Generator TCLK B8ZS/HDB3 TPOS Unipolar TNEG Encoder Encoder Enable Remote Decoder Loopback Enable RLOOP Enable Jitter JASEL Attenuator B8ZS/HDB3 RPOS Unipolar ...
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... Dual Loopback (DLOOP) enables simultaneous loopbacks to both the framer and the line. The TCLK, TPOS and TNEG framer inputs are routed through the jitter attenuator and looped back to the RCLK, RPOS and RNEG outputs. The RTIP/RRING line inputs are looped back through the timing recovery block and line driver onto the TTIP/TRING outputs ...
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Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation — LXT332 1.2.2 Bipolar Violation Insertion The same pins which provide the high frequency clocks can also be used to insert bipolar violations into the outgoing data stream. Violations can be ...
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LXT332 — Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation 2.0 Pin Assignments and Signal Descriptions Figure 2 and Figure 3 Note that many pins have two functions. The active function is determined by the particular mode of operation ...
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Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation — LXT332 Figure 3. LXT332 Pin Assignments and Package Markings (QFP Package RCLK0 2 TAOS0 / SCLK 3 LEN20 ...
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... Description Tristate Output Enable. When held High, forces all output pins to high-Z (tri-state). When held Low, Bipolar I/O mode is selected. In this mode, the framer interface is bipolar (TPOS/TNEG and RPOS/RNEG), and the B8ZS/HDB3 encoders are disabled. When clocked by MCLK, Unipolar I/O mode is selected. In this mode, the framer interface is unipolar (TDATA and RDATA), and the TNEG and RNEG pins are re- mapped ...
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Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation — LXT332 Table 1. Host Mode and Bipolar Host Mode Pin Descriptions (Continued) Pin Pin 1 Symbol I/O QFP PLCC 7 13 GND TTIP0 TRING0 ...
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LXT332 — Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation Table 1. Host Mode and Bipolar Host Mode Pin Descriptions (Continued) Pin Pin 1 Symbol I/O QFP PLCC 28 34 JASEL VCQ1 DI SPE ...
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... Tristate Output Enable. When held High, forces all output pins to high-Z (tri-state). When held Low, Bipolar I/O mode is selected. In this mode, the framer interface is bipolar (TPOS/TNEG and RPOS/RNEG), and the B8ZS/HDB3 encoders are disabled. When clocked by MCLK, Unipolar I/O mode is selected. In this mode, the framer interface is unipolar (TDATA and RDATA), and the TNEG and RNEG pins are re- mapped ...
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... Remote Loopback Enable - Port 0. When High, the clock and data inputs (from the framer) are ignored and the data received from the twisted-pair line is transmitted back onto the line at the RCLK frequency. Note that if LLOOP is High, Remote Loopback is inhibited (on the respective port). ...
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Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation — LXT332 Table 3. Hardware Mode and Bipolar Hardware Mode Pin Descriptions Pin Pin 2 Symbol I/O QFP PLCC 33 39 RCLK1 DO RPOS1 (Bipolar) RNEG1 35 41 ...
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... The integrated crystal-less jitter attenuator may be positioned in either the transmit or receive path, or disabled. Each DLIU transceiver back-end interfaces with a framer through either bipolar or unipolar data I/ O channels. The DLIU may be controlled by a microprocessor through the serial port (Host mode hard-wired pins for stand-alone operation (Hardware mode). ...
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... The two transmitters in the LXT332 DLIU are identical. The following paragraphs describe the operation of a single transmitter. Transmit data from the framer is clocked serially into the device at TPOS/TNEG in the bipolar mode or at TDATA in the unipolar mode. The transmit clock (TCLK) supplies the input synchronization ...
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LXT332 — Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation 3. During Remote Loopback, BPV insertion is disabled. A Low-to-High transition on VCQ is required for each subsequent BPV insertion. 3.2.2 Pulse Shape The transmitted pulse shape is determined ...
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Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation — LXT332 3.4 Jitter Attenuation A digital Jitter Attenuation Loop (JAL) combined with an Elastic Store (ES) provides jitter attenuation. The JAL is internal and requires no external crystal nor high-frequency ...
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LXT332 — Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation The LIU, selected by the PS pulse, responds by writing the incoming serial word from the SDI pin into its command register 8-bit Command/Address byte and an ...
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Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation — LXT332 Table 7. SIO Input Bit Settings (See Figure 5) Mode Remote Loopback Local Loopback Dual loopback Transmit all ones Reset Table 8. LXT332 Serial Data Output Bit Coding (See ...
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LXT332 — Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation Figure 5. LXT332 SIO Write Operation PS SCLK ADDRESS COMMAND BYTE R SDI SDO: remains high impedance ADDRESS / COMMAND R/W A0 BYTE ...
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Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation — LXT332 Figure 7. LX332 Interrupt Handling Start-up or Reset Interrupts Enabled INT* = High No (No Interrupt) INT* = Low (Interrupt) Read Output Status Word* Read Output Status Word* (bits ...
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LXT332 — Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation 3.7.3 Interrupt Handling The Host mode provides two latched Interrupt output pins, INT0 and INT1, one for each LIU port. An interrupt is triggered by a change in the ...
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Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation — LXT332 Figure 8. TAOS Data Path 3.9.2 Local Loopback (See Figure 9 and Figure 10) Local Loopback (LLOOP) is selected when LLOOP = 1 and RLOOP = 0. In LLOOP ...
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LXT332 — Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation Figure 10. Local Loopback - Selectable JA 3.9.3 Remote Loopback (See Figure 11) Remote Loopback (RLOOP) is selected when RLOOP = 1 and LLOOP = 0. Note that TAOS ...
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Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation — LXT332 Figure 11. Remote Loopback - Selectable JA 3.9.4 Dual Loopback (See Figure 12) Dual Loopback (DLOOP) is selected when RLOOP = 1, LLOOP = 1 and TAOS = 1. ...
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LXT332 — Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation High on one of these pins triggers QRSS pattern transmission from the appropriate port. The QRSS pattern for DSX-1 systems is 2 systems the QRSS pattern is 2 transmission ...
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... Driving JASEL Low switches the jitter attenuation circuits into the transmit paths for both LIU ports. Figure 14 shows a pair of framers (a dual framer could also be used). A LXP600A Clock Adapter (CLAD) converts the 2.048 MHz backplane clock to provide the 1.544 MHz input to the MCLK and TCLK inputs of both LIU ports. ...
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LXT332 — Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation The line interface circuitry is identical for both LIU ports. The precision resistors in line with the transmit transformer provide optimal return loss. The recommended transformer/resistor combinations are listed ...
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Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation — LXT332 Figure 14. Typical LXT332 T1 Application (Host Control Mode, Bipolar I/O) LXP600A 2.048 MHz CLKI 1.544 MHz CLKO TCLK TPOS0 TNEG0 RPOS0 RNEG0 RCLK0 TPOS1 TNEG1 TCLK1 RPOS1 RNEG1 ...
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LXT332 — Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation 4.5 2.048 Mbps E1/CEPT Interface Applications 4.5.1 E1 Coaxial Applications Figure 15 shows the line interface for a typical 2.048 Mbps E1 coaxial (75 ) application. The LEN code ...
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Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation — LXT332 Figure 16. Typical LXT332 E1 120 2.048 MHz Clock Source TCLK TPOS0 TNEG0 RPOS0 RNEG0 RCLK0 TPOS1 TNEG1 RPOS1 RNEG1 RCLK1 NOTES: 1. Transformer turns ratio accuracy is ±2%. ...
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LXT332 — Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation 5.0 Test Specifications Note: Information in Table 11 performance specifications of the LXT332 Dual Line Interface Unit and are guaranteed by test, except as noted, by design. Table 11. ...
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Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation — LXT332 Table 13. Electrical Characteristics (Over Recommended Operating Conditions) (Continued) Parameter 2 Three-state leakage current 5 Input pull down current (MCLK) TTIP/TRING leakage current 1. Total power dissipation includes the ...
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LXT332 — Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation Table 14. Analog Specifications (Over Recommended Operating Conditions) (Continued) Parameter Allowable consecutive zeros before LOS T1 Jitter attenuation curve corner 2,3 frequency E1 Attenuation input jitter tolerance before 3 ...
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Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation — LXT332 Figure 18. LXT332 Serial Data Output Timing Diagram PS SCLK t CDV SDO CLKE = 1 t CDV SDO CLKE = 0 Figure 19. LXT332 Receive Clock Timing t ...
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LXT332 — Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation Table 16. LXT332 Receive Timing Characteristics (See Figure 19) Parameter DSX-1 Receive clock period E1 Receive clock duty cycle DSX-1 Receive clock pulse width High E1 DSX-1 Receive clock ...
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Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation — LXT332 Figure 21. Typical Receiver Input Jitter Tolerance (Loop Mode) 1000 UI 100 4.9 Hz AT&T 62411, Dec 1990 (T1 1 ...
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LXT332 — Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation Figure 22. Typical Jitter Transfer Performance E1 Jitter 10 dB Transfer Performance 0 dB -10 dB -20 dB -30 dB - Jitter Transfer ...
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Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation — LXT332 6.0 Mechanical Specifications Figure 23. LXT332 PLCC Package Specifications Datasheet Plastic Leaded Chip Carrier (PLCC) • Part Number LXT322PE ...
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LXT332 — Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation Figure 24. LXT332 QFP Package Specifications Dim ...