SLXT332QE.G2 S E001 Intel, SLXT332QE.G2 S E001 Datasheet - Page 11

• Manufacturer Part Number: SLXT332QE.G2 S E001
• Manufacturer: Intel

Specifications of SLXT332QE.G2 S E001

• Operating Supply Voltage (typ): 5V
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Datasheet
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output; S = Power
QFP
Pin
10
12
13
14
15
16
17
18
19
20
21
22
23
26
24
25
27
11
7
8
9
Supply.
Table 1. Host Mode and Bipolar Host Mode Pin Descriptions (Continued)
PLCC
Pin
13
14
17
15
16
18
19
20
21
22
23
24
25
26
27
28
29
32
30
31
33
RRING0
RRING1
Symbol
TRING0
TRING1
TGND0
TGND1
TVCC0
TVCC1
RTIP0
RTIP1
TTIP0
CLKE
TTIP1
GND
DFM
VCC
PS0
PD0
PD1
PS1
SDI
Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation — LXT332
I/O
AO
AO
DO
DO
DO
AO
AO
DI
DI
DI
DI
AI
AI
AI
AI
S
S
S
S
S
S
1
Ground. Ground return for the VCC power supply.
Transmit Tip and Ring - Port 0. These pins are differential driver outputs designed to
drive a 35 - 200
give the desired pulse height. See
details.
Ground - Port 0 Transmit Driver. Ground return for the TVCC0 power supply.
+ 5 VDC - Port 0 Transmit Driver. TVCC0 must not vary from TVCC1 or VCC by more
than ± 0.3 V.
Driver Failure Monitor. This signal goes High to indicate a driver output short in one
or both ports.
Port Select - Port 0. This signal selects the serial interface registers for port 0. For
each read or write operation, PS0 must transition from High to Low, and remain Low.
Pattern Detect - Port 0. Unless the QRSS function is selected by the VCQE pin, PD0
functions as an Alarm Indication Signal (AIS). The AIS pattern is detected by the
receiver, independent of any loopback mode. PD0 goes High when less than three
zeros have been detected in any string of 2048 bits. PD0 returns Low when the
received signal contains more than three zeros in 2048 bits.
If the QRSS function is enabled by the VCQE pin, PD0 remains High until pattern sync
is reached with the received signal. Once pattern lock is obtained, PD0 goes Low. The
sync/out-of-sync criteria is: less than 3/4 errors in 128 bits. After sync acquisition, bit
errors cause PD0 to go High for half a clock cycle. PD0 can be used to trigger an
external error counter.
Receive Tip and Ring - Port 0. These pins comprise the receive line interface and
should be connected to the line through a center-tapped 1:2 transformer. See
14
Clock Edge Select. When CLKE is High, RPOS/RNEG or RDATA outputs are valid on
the falling edge of RCLK, and SDO is valid on the rising edge of SCLK.
When CLKE is Low, RPOS/RNEG or RDATA outputs are valid on the rising edge of
RCLK, and SDO is valid on the falling edge of SCLK.
Receive Tip and Ring - Port 1. These pins comprise the receive line interface and
should be connected to the line through a center-tapped 1:2 transformer. See
through
Pattern Detect - Port 1. Reports AIS and QRSS pattern reception. See PD0 signal
description for details.
Serial Data Input. Write data to the LXT332 registers is input on this pin. SDI is
sampled on the rising edge of SCLK.
Port Select - Port 1. Selects the serial interface registers for port 1. For each read or
write operation, PS1 must transition from High to Low, and remain Low.
Transmit Tip and Ring - Port 1. These pins are differential driver outputs designed to
drive a 35 - 200
give the desired pulse height. See
details.
+ 5 VDC - Port 1 Transmit Driver. TVCC1 must not vary from TVCC0 or VCC by more
than ± 0.3 V.
Ground - Port 1 Transmit Driver. Ground return for the TVCC1 power supply.
+5 VDC. Power supply for all circuits except the transmit drivers.
through
Figure 16
Figure 16
for details.
load. Line matching resistors and transformers can be selected to
load. Line matching resistors and transformers can be selected to
for details.
Table 10
Table 10
Description
and
and
Figure 14
Figure 14
through
through
Figure 16
Figure 16
Figure 14
for
for
Figure
11