SLXT332QE.G2 S E001 Intel, SLXT332QE.G2 S E001 Datasheet - Page 28

• Manufacturer Part Number: SLXT332QE.G2 S E001
• Manufacturer: Intel

Specifications of SLXT332QE.G2 S E001

• Operating Supply Voltage (typ): 5V
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

LXT332 — Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation
3.10
28
Figure 13. QRSS BIST
High on one of these pins triggers QRSS pattern transmission from the appropriate port. The
QRSS pattern for DSX-1 systems is 2
systems the QRSS pattern is 2
transmission is activated, errors can be inserted into the transmit data stream by causing a Low-to-
High transition on the TPOS/TDATA pin for the respective port.
In Bipolar I/O mode, Low-High transitions cause both a logic error and a bipolar violation to be
inserted into the QRSS data stream. In Unipolar I/O mode, only a logic error is inserted.
The Pattern Detect circuitry is activated by the QRSS BIST function, although the basic receive
circuits are unaffected. The Pattern Detect pins (PD0 and PD1) indicate QRSS pattern sync for the
respective LIU port. The PD pin stays High until synchronization is achieved on the QRSS pattern.
The QRSS pattern is considered in sync when there are fewer than 4 errors in 128 bits. The PD pin
goes High indicating an out-of-sync condition if 4 or more errors are detected in 128 bits (i.e. sync
is defined as fewer than 4 errors in 128 bits).
Initialization/Reset Operation
Upon initial power up, the transceiver is held static until the power supply reaches approximately 3
V. Upon crossing this threshold, the device clears all internal registers and begins calibration of the
delay lines. A reference clock is required to calibrate the delay lines. TCLK is the transmit
reference, and MCLK is the receive reference. The PLLs are continuously calibrated.
The transceiver can be reset from either the Host or Hardware mode. In Host mode, reset is
commanded by writing 1s to RLOOP and LLOOP, and a 0 to TAOS (bits D5, D6 and D7,
respectively, of the SIO input data byte). In Hardware mode, reset is commanded by
simultaneously holding RLOOP and LLOOP High, and TAOS Low, for approximately 200 ns.
Reset is initiated on the falling edge of the reset request. In either mode, each port may be reset
independently. Reset clears and sets all SIO registers, of the selected port, to 0. Reset is not
generally required for the port to be operational.
TNEG
TPOS
TCLK
RCLK
RNEG
RPOS
MCLK
PD
(CLKE = 1)
RCLK
RCLK
(CLKE = 0)
PD
Receive QRSS
Pattern Lock
15
QRSS BIST =
-1. The QRSS pattern is locked to MCLK. Once the QRSS
20
QRSS Pattern Generator
QRSS Sync/Error Detector
-1, with no more than 14 consecutive zeros. For CEPT
3
3
Clocked
VCQE
Low-to-High transition
Recovery
Timing &
Timing
Control
VCQ0/1
Receive QRSS
Logic Error
Detected
TTIP
TRING
RTIP
RRING
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