TP11368V63SN National Semiconductor, TP11368V63SN Datasheet - Page 5

• Manufacturer Part Number: TP11368V63SN
• Manufacturer: National Semiconductor

Specifications of TP11368V63SN

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
by a receive (decoder) operation. For the encoding opera-
tion, the PCM data is stored in the 8-bit shift register at the
falling edge of CE while TRB is high. The TP11368 pro-
cesses the data within 123 CLK periods during the following
cycle of CE. The encoded ADPCM data is loaded into the
5-bit parallel-to-serial output register with the falling edge of
CE. The MSB data is shifted out first with the leading edge of
CE, and subsequent data is shifted out with the rising edge
of ASCK. For the decoding operation, the ADPCM data is
(Continued)
FIGURE 3. Serial Output Structure
5
latched and transferred to the core at the falling edge of CE
while TRB is low. The data is processed within 123 CLK pe-
riods and the decoded 8-bit PCM data is shifted out with the
MSB first.
PSCK and ASCK are the clocks for the PCM and ADPCM
data streams, respectively. They must be high during the
transition of CE. Note that PSCK and ASCK are shown as
gated clocks as an option to conserve power. PSCK and
ASCK need only be valid while CE is high.
DS012902-5
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