TP11368V63SN National Semiconductor, TP11368V63SN Datasheet - Page 9

• Manufacturer Part Number: TP11368V63SN
• Manufacturer: National Semiconductor

Specifications of TP11368V63SN

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
CHANNEL NOP
Each channel can be independently disabled. When EN is at
logic low on the falling edge of CE, the ADPCM transcoder
processing for that channel is disabled. The processor re-
quires 4 CLK cycles for CE to maintain all channel variables.
The data output ports are also placed in known states. After
this the processor waits for the next interrupt. TSO outputs
the following data after a channel NOP:
The data pattern at TSO in Table 6 are shown with four
ASCK clocks within the CE high pulse for the 32- , 24-,
16-kbps modes and five ASCK clocks within the CE high
pulse for the 40 kbps mode. In the case where ASCK pulses
are more than four or five, the given pattern recirculates with
the MSB first.
In the idle state, RSO outputs the following data (bit repre-
sentation with the sign-bit on the left followed by the MSB,
the sign-bit is the first bit after the rising edge of CE):
QSEL1
PCM1
0
0
1
1
0
1
TABLE 7. RSO at Channel NOP
TABLE 6. TSO at Channel NOP
QSEL0
8-Bit A-Law
8-Bit µ-Law
0
1
0
1
Mode
32 kbps
24 kbps
16 kbps
40 kbps
Mode
1 1 1 1 1 1 1 1
1 1 0 1 0 1 0 1
(Continued)
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0 0
RSO
TSO
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