DP83932CVF25 National Semiconductor, DP83932CVF25 Datasheet - Page 50

• Manufacturer Part Number: DP83932CVF25
• Manufacturer: National Semiconductor

Specifications of DP83932CVF25

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Mounting: Surface Mount
• Pin Count: 132
• Lead Free Status / RoHS Status: Not Compliant

SHARED-MEMORY ACCESS PINS
USER DEFINABLE PINS
POWER AND GROUND PINS
MREQ
SMACK
USR0 1
VCC1 –5
VCCL
TXVCC
RXVCC
PLLVCC
GND1–6
GNDL
TXGND
ANGND
5 0 Bus Interface
5 3 SYSTEM CONFIGURATION
Any device that meets the SONIC interface protocol and
electrical requirements (timing threshold and loading) can
be interfaced to SONIC Since two bus protocols are provid-
ed via the BMODE pin the SONIC can interface directly to
most microprocessors Figure 5-3 shows a typical interface
to the National Intel style bus (BMODE
shows a typical interface to the Motorola style bus
(BMODE
The BMODE pin also controls byte ordering
BMODE
BMODE
Symbol
e
e
e
1 big endian byte ordering is selected and when
0 little endian byte ordering is selected
1)
Driver
Type
TRI
TP
Direction
(Continued)
I O Z
O
I
e
Memory Request The system asserts this signal low when it attempts to access the
shared-buffer RAM The on-chip arbiter resolves accesses between the system and the
SONIC
Note Both CS and MREQ must not be asserted concurrently If these signals are
successively asserted there must be at least two bus clocks between the deasserting
edge of the first signal and the asserting edge of the second signal
In Motorola mode if a bus master uses the MREQ to request the bus from the SONIC
care should be taken to isolate the DSACK0 1 from the bus (e g use tri-state buffers)
because the DSACK0 1 will be driven by the SONIC even after the SONIC has given up
the bus
Slave and Memory Acknowledge SONIC asserts this dual function pin low in
response to either a Chip Select (CS) or a Memory Request (MREQ) when the SONIC’s
registers or its buffer memory is available for accessing This pin can be used for
enabling bus drivers for dual-bus systems
User Define 0 1 These signals are inputs when SONIC is hardware reset and are
outputs when SONIC is a bus master (HLDA or BGACK asserted) When hard reset
(RST) is low these signals input directly into bits 8 and 9 of the Data Configuration
register (DCR) respectively The levels on these pins are latched on the rising edge of
RST During busmaster operations (HLDA or BGACK is active) these pins are outputs
whose levels are programmable through bits 11 and 12 of the DCR respectively The
USR0 1 pins should be pulled up to V
resistor is recommended
Power The
Power These pins are the
must be tied to V
Ground The ground reference for the digital portions of the SONIC
Ground These pins are the ground references for the SONIC ENDEC unit These pins
must be tied to ground even if the internal ENDEC is not used
0) and Figure 5-4
TABLE 5-1 Pin Description (Continued)
a
When
5V power supply for the digital portions of the SONIC
CC
even if the internal ENDEC is not used
50
5 4 BUS OPERATIONS
There are two types of system bus operations 1) SONIC as
a slave and 2) SONIC as a bus master When SONIC is a
slave (e g a CPU accessing SONIC registers) all transfers
are non-DMA When SONIC is a bus master (e g SONIC
accessing receive or transmit buffer descriptor areas) all
transfers are block transfers using SONIC’s on-chip DMA
This section describes the SONIC bus operations Pay spe-
cial attention to all sections labeled as ‘‘Note’’ These con-
ditions must be met for proper bus operation
a
5V power supply for the SONIC ENDEC unit These pins
CC
Description
or pulled down to ground A 4 7 k
pull-up