DP83932CVF25 National Semiconductor, DP83932CVF25 Datasheet - Page 87

• Manufacturer Part Number: DP83932CVF25
• Manufacturer: National Semiconductor

Specifications of DP83932CVF25

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Mounting: Surface Mount
• Pin Count: 132
• Lead Free Status / RoHS Status: Not Compliant

7 0 AC and DC Specifications
MEMORY ARBITRATION SLAVE ACCESS
Note 1 Both CS and MREQ must not be asserted concurrently If these signals are successively asserted there must be at least two bus clocks between the
deasserting and asserting edges of these signals
Note 2 It is not necessary to meet the setup times for MREQ or CS since these signals are asynchronously sampled Meeting the setup time for these signals
however makes it possible to use T60 to determine when SMACK will be asserted
Note 3 T60 could range from 1 bus clock minimum to 5 bus clock maximum depending on what state machine the SONIC is in when the CS or MREQ signal is
asserted This timing is not tested but is guaranteed by design This specification assumes that CS or MREQ is asserted before the falling edge that these signals
are asynchronously clocked in on (see T56 and T58) SAS must have been asserted for this timing to be correct See SAS and CS timing in the Register Read and
Register Write timing specifications
Note 4 bcyc
Note 5 The way in which SMACK is asserted due to CS is not the same as the way in which SMACK is asserted due to MREQ SMACK goes low as a direct result
of the assertion of MREQ whereas for CS SAS must also be driven low (BMODE
when SMACK is asserted due to MREQ SMACK will remain asserted until MREQ is deasserted Multiple memory accesses can be made to the shared memory
without SMACK ever going high When SMACK is asserted due to CS however SMACK will only remain low as long as SAS is also low (BMODE
(BMODE
important difference to consider when designing shared memory designs
Number
T56
T58
T60
T80
T81
e
0) SMACK will not remain low throughout multiple register accesses to the SONIC because SAS must toggle for each register access This in an
e
bus clock cycle time (T3)
CS Low Asynch Setup to BSCK
(Note 2)
MREQ Low Asynch Setup to BSCK
(Note 2)
MREQ or CS Valid to SMACK Low
(Notes 3 4)
MREQ to SMACK High
BSCK to SMACK Low
Parameter
(Continued)
Min
8
8
1
20 MHz
87
e
Max
1) or high (BMODE
18
22
5
Min
7
7
1
25 MHz
e
0) before SMACK will be asserted This means that
Max
16
20
5
Min
6
6
1
33 MHz
Max
14
18
5
TL F 10492 – 70
e
1) or high
Units
bcyc
ns
ns
ns
ns