ISP1506ABS,557 NXP Semiconductors, ISP1506ABS,557 Datasheet - Page 48

• Manufacturer Part Number: ISP1506ABS,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1506ABS,557

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 27.
Table 28.
ISP1506A_ISP1506B_2
Product data sheet
Bit
7
6
5
4
3
2
1
0
Bit
Symbol
Reset
Access
Symbol
INTF_PROT_DIS
IND_PASSTHRU
IND_COMPL
-
CLOCK_
SUSPENDM
-
3PIN_FSLS_
SERIAL
-
Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit description
OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit allocation
USE_EXT_
VBUS_IND
10.1.4 OTG Control register
R/W/S/C
7
0
This register controls various OTG functions of the ISP1506. The bit allocation of the OTG
Control register is given in
Description
Interface Protect Disable: Controls circuitry built into the ISP1506 to protect the ULPI interface
when the link 3-states STP and DATA[3:0]. When this bit is enabled, the ISP1506 will
automatically detect when the link stops driving STP.
0b — Enables the interface protect circuit (default). The ISP1506 attaches a weak pull-up
resistor on STP. If STP is unexpectedly HIGH, the ISP1506 attaches weak pull-down resistors
on DATA[3:0], protecting data inputs.
1b — Disables the interface protect circuit, detaches weak pull-down resistors on DATA[3:0],
and a weak pull-up resistor on STP.
Indicator Pass-through: The ISP1506 does not support the qualification of an external FAULT
with the internal V
or the V
logic 1.
0b — Not supported.
1b — The complement output signal is not qualified with the internal A_VBUS_VLD comparator.
The link must always set this bit to logic 1.
Indicator Complement: Informs the PHY to invert the FAULT input signal, generating the
complement output. For details, see
0b — The ISP1506 will not invert the FAULT signal (default).
1b — The ISP1506 will invert the FAULT signal.
reserved
Clock Suspend LOW: Active LOW clock suspend.
Powers down the internal clock circuitry only. By default, the clock will not be powered in 3-pin
serial mode.
Valid only in 3-pin serial mode. Valid only when SUSPENDM is set to logic 1, otherwise this bit
is ignored.
0b — Clock will not be powered in 3-pin serial mode (default).
1b — Clock will be powered in 3-pin serial mode.
reserved
3-Pin Full-Speed Low-Speed Serial Mode: Changes the ULPI interface to a 3-bit serial
interface. The PHY will automatically clear this bit when 3-pin serial mode is exited.
0b — Full-speed or low-speed packets are sent using the parallel interface (default).
1b — Full-speed or low-speed packets are sent using the 3-pin serial interface.
reserved
VBUS_EXT
R/W/S/C
DRV_
6
0
BUS
power is connected to the V
R/W/S/C
DRV_
VBUS
A_VBUS_VLD
5
0
Rev. 02 — 28 August 2008
Table
R/W/S/C
comparator. Either a digital FAULT is input on the V
CHRG_
VBUS
4
0
28.
Section
BUS
DISCHRG_
R/W/S/C
/FAULT pin, not both. This bit must always be set to
9.5.2.2.
VBUS
3
0
ISP1506A; ISP1506B
DM_PULL
R/W/S/C
DOWN
ULPI HS USB OTG transceiver
2
1
DP_PULL
R/W/S/C
DOWN
1
1
© NXP B.V. 2008. All rights reserved.
BUS
/FAULT pin
ID_PULL
R/W/S/C
UP
0
0
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