ISP1506ABS STEricsson, ISP1506ABS Datasheet
ISP1506ABS
Specifications of ISP1506ABS
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ISP1506ABS Summary of contents
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IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - NXP ...
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ISP1506A; ISP1506B ULPI Hi-Speed USB OTG transceiver Rev. 02 — 28 August 2008 1. General description The ISP1506 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver that is fully compliant with Supplement to the USB 2.0 Specification Rev. 1.3” ...
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... N Supports 4-bit dual-edge data bus N Supports 60 MHz output clock configuration N Integrated Phase-Locked Loop (PLL), supporting one crystal or clock frequency: 19.2 MHz (ISP1506ABS) and 26 MHz (ISP1506BBS) N Fully programmable ULPI-compliant register set N Internal Power-On Reset (POR) circuit I Flexible system integration and very low current consumption, optimized for portable ...
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... I Video camera 4. Ordering information Table 1. Ordering information Part Type number Marking Crystal or clock frequency [1] ISP1506ABS 06A 19.2 MHz [1] ISP1506BBS 06B 26 MHz [1] The package marking is the first line of text on the IC package and can be used for IC identification. ISP1506A_ISP1506B_2 Product data sheet Package ...
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NXP Semiconductors 5. Block diagram 19 CLOCK 17 STP 16 DIR ULPI INTERFACE 18 NXT 20, 22, 23 DATA[3:0] 14 RESET_N/ PSW_N global clocks 12 XTAL1 13 XTAL2 CC(I/O) 11 REG3V3 15 REG1V8 9 V ...
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NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description Table 2. Pin description [1][2][3] [4] Symbol Pin Type CC(I/O) RREF CPGND 6 P ...
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NXP Semiconductors Table 2. Pin description …continued [1][2][3] [4] Symbol Pin Type RESET_N/ 14 I/O PSW_N REG1V8 15 P DIR 16 O STP 17 I NXT 18 O CLOCK 19 O DATA3 20 I CC(I/O) DATA2 22 ...
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NXP Semiconductors 7. Functional description 7.1 ULPI interface controller The ISP1506 provides an 8-pin interface that is compliant with Interface (ULPI) Specification Rev. The ULPI interface controller provides the following functions: • ULPI compliant and register set • Allows full ...
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NXP Semiconductors • Squelch circuit to detect high-speed bus activity • High-speed disconnect detector • 45 • 1.5 k pull-up resistor on DP for full-speed peripheral mode • bus terminations on DP and DM for host and OTG ...
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NXP Semiconductors • Charge pump to provide 5 V power on V power from the ISP1506 V 7.6.1 ID detector The ID detector detects which end of the micro-USB cable is plugged in. The detector must first be enabled by ...
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NXP Semiconductors which also shows a typical OTG V amount of current drive required. If the internal charge pump is not used, the C capacitor is not required. For details on the C_A and C_B pins, see Fig 3. 7.7 ...
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NXP Semiconductors • STP 7.9.3 RREF Resistor reference analog I/O pin. A resistor, R and GND, as shown in biases internal analog circuitry. Less accurate resistors cannot be used and will render the ISP1506 unusable. 7.9.4 DP and DM DP ...
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NXP Semiconductors Table 3. C cp(C_A)-(C_B 270 nF 7.9 the main input supply voltage for the ISP1506. Decoupling capacitors are CC recommended. For details, see 7.9.9 V /FAULT BUS This pin provides two options ...
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NXP Semiconductors 7.9.12 RESET_N/PSW_N This pin provides two optional functions. If neither function is used, this pin must be connected to V 7.9.12.1 RESET_N An active LOW asynchronous reset pin that resets all circuits in the ISP1506. The ISP1506 contains ...
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NXP Semiconductors 7.9.15 NXT ULPI next data output pin. The ISP1506 holds NXT at LOW by default. When DIR is LOW and the link is sending data to the ISP1506, NXT will be asserted to notify the link to provide ...
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NXP Semiconductors 8. Modes of operation 8.1 ULPI modes The ISP1506 ULPI bus can be programmed to operate in three modes. Each mode reconfigures the signals on the data bus as described in the following subsections. Setting more than one ...
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NXP Semiconductors Table 4. ULPI signal description Signal name Direction on Signal description ISP1506 DIR O Direction: Controls the direction of data bus DATA[3:0]. In synchronous mode, the ISP1506 drives DIR to LOW by default, making the data bus an ...
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NXP Semiconductors 8.1.3 3-pin full-speed or low-speed serial mode If the link requires a 3-pin serial interface to transmit and receive full-speed or low-speed USB data, it can set the ISP1506 to 3-pin serial mode. In 3-pin serial mode, the ...
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NXP Semiconductors Table 7. Operating states and their corresponding resistor settings Signaling mode Register settings XCVR SELECT [1:0] General settings 3-state drivers XXb Power-up or 01b V < V BUS B_SESS_END Host settings Host chirp 00b Host high-speed 00b Host ...
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NXP Semiconductors Table 7. Operating states and their corresponding resistor settings Signaling mode Register settings XCVR SELECT [1:0] OTG device 01b peripheral high-speed and full-speed suspend OTG device 01b peripheral high-speed and full-speed resume OTG device 00b peripheral Test J ...
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NXP Semiconductors 9. Protocol description The following subsections describe the protocol for using the ISP1506. Remark: In all figures, the ULPI data is shown in a generic form and not as nibbles on the rising and falling edges of the ...
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NXP Semiconductors completed. After every reset, an RXCMD is sent to the link to update USB status information. After this sequence, the ULPI bus is ready for use and the link can start USB operations. When the internal PLL is ...
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NXP Semiconductors CC(I/O) REG1V8 t PWRUP internal REG1V8 detector internal POR XTAL1 CLOCK DATA[3:0] DIR STP NXT and V are applied to the ISP1506. The ISP1506 regulator starts to turn on. CC ...
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NXP Semiconductors The interface protect feature prevents unwanted activity of the ISP1506 whenever the ULPI interface is not correctly driven by the link. For example, when the link powers up more slowly than the ISP1506. The interface protect feature can ...
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NXP Semiconductors Table 8. DRV_VBUS 9.4.2 Fault detection The ISP1506 supports external V indicator signal. The indicator signal must be connected to the FAULT pin. To enable the ISP1506 to monitor the digital fault input, the link ...
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NXP Semiconductors 9.5.2 RXCMD The ISP1506 communicates status information to the link by asserting DIR and sending an RXCMD byte on the data bus. The RXCMD data byte format is given in The ISP1506 will automatically send an RXCMD whenever ...
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NXP Semiconductors Table 11. LINESTATE[1:0] encoding for upstream facing ports: peripheral [1] DP_PULLDOWN = 0. Mode Full-speed XCVRSELECT[1:0] 01, 11 TERMSELECT 1 LINESTATE[1:0] 00 SE0 01 FS-J 10 FS-K 11 SE1 [1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output. ...
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NXP Semiconductors V /FAULT BUS IND_COMPL USE_EXT_VBUS_IND, IND_PASSTHRU Fig 9. RXCMD A_VBUS_VLD indicator source 9.5.2.3 Using and selecting the V The V BUS link whenever there is a change in the V must first enable the corresponding interrupts in the ...
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NXP Semiconductors OTG devices: provide a minimum there is no need for an overcurrent detection circuit because the internal A_VBUS_VLD comparator is sufficient. If the OTG A-device provides more than 100 overcurrent ...
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NXP Semiconductors 9.6 Register read and write operations Figure 10 addressing and extended addressing register operations. Extended register addressing is optional for links. Note that register operations will be aborted if the ISP1506 unexpectedly asserts DIR during the operation. When ...
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NXP Semiconductors than 7 ms after reset time T up its clock within 5.6 ms, leaving 200 s for the link to start transmitting the Chirp K, and 1.2 ms for the Chirp K to complete (worst case with 10 ...
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NXP Semiconductors USB reset T 0 TXCMD (REGW) SE0 DATA [ 3:0 ] DIR STP NXT 01 (FS) XCVR SELECT TERM SELECT 00 (normal) OP MODE SE0 (00b) J (01b) LINE STATE TXCMD (REGW) SE0 DATA [ 3:0 ] DIR ...
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NXP Semiconductors 9.8 USB packet transmit and receive An example of a packet transmit and receive is shown in packets, refer to link sends TXCMD CLOCK DATA [ 3:0 ] TXCMD DIR STP NXT Fig 12. Example of using the ...
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NXP Semiconductors Table 17. Link decision times Packet sequence High-speed link delay Transmit-Transmit (host only) Receive-Transmit (host or peripheral) Receive-Receive 1 (peripheral only) Transmit-Receive 92 (host or peripheral DATA DM CLOCK D ...
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NXP Semiconductors DP or DATA EOP DM CLOCK DATA [3: DIR STP NXT RX end delay (three to eight clocks) Fig 14. High-speed receive-to-transmit packet timing 9.9 ...
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NXP Semiconductors CLOCK DATA[3: Fig 15. Preamble sequence 9.10 USB suspend and resume 9.10.1 Full-speed or low-speed host-initiated suspend and resume Figure 16 suspend and sometime later initiates resume signaling to wake up the downstream peripheral. Note ...
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NXP Semiconductors idle DATA [ 3:0 ] DIR STP NXT OPMODE 00b LINE J STATE CLOCK TXCMD (REGW) DATA [ 3:0 ] DIR STP NXT OPMODE SUSPENDM LINE STATE DP DM Timing is not to scale. Fig 16. Full-speed suspend ...
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NXP Semiconductors The sequence of events related to a host and a peripheral, both with ISP1506 follows. 1. High-speed idle: Initially, the host and the peripheral are idle. The host has its 15 k pull-down resistors enabled (DP_PULLDOWN ...
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NXP Semiconductors HS idle TXCMD (REGW) DATA [ 3:0 ] DIR STP NXT XCVR 00b SELECT TERM SELECT OP MODE !squelch squelch (01b) (00b) LINE STATE CLOCK TXCMD (REGW) DATA [ 3:0 ] DIR STP NXT XCVR 00b SELECT TERM ...
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NXP Semiconductors 9.10.3 Remote wake-up The ISP1506 supports peripherals that initiate remote wake-up resume. When placed into USB suspend, the peripheral link remembers at what speed it was originally operating. Depending on the original speed, the link follows one of ...
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NXP Semiconductors LINESTATE DATA [ 3:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE TXCMD LINESTATE REGW DATA [ 3:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE Timing is not to scale. Fig 18. Remote ...
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NXP Semiconductors PHY will not transmit any EOP. The ISP1506 will also detect if the PID byte is A5h, indicating an SOF packet, and automatically send a long EOP when STP is asserted. To transmit chirp and resume signaling, the ...
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NXP Semiconductors 9.12.1 OTG charge pump A description of the charge pump is given in configured as an A-device, it can provide the V Control of the charge pump is described in 9.12.2 OTG comparators The ISP1506 provides comparators that ...
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NXP Semiconductors SYNC DATA0 (TX_ENABLE) DATA1 (DAT) DATA2 (SE0 Fig 20. Example of transmit followed by receive in 3-pin serial mode 9.14 Aborting transfers The ISP1506 supports aborting transfers on the ULPI bus. For details, refer to “UTMI+ ...
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NXP Semiconductors 10. Register map Table 18. Immediate register set overview Field name Vendor ID Low register Vendor ID High register Product ID Low register Product ID High register Function Control register Interface Control register OTG Control register USB Interrupt ...
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NXP Semiconductors 10.1 Immediate register set 10.1.1 Vendor ID and Product ID registers 10.1.1.1 Vendor ID Low register Table 20 Table 20. Vendor ID Low register (address R = 00h) bit description Bit Symbol Access VENDOR_ID_ R ...
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NXP Semiconductors Table 25. Function Control register (address R = 04h to 06h 04h 05h 06h) bit description Bit Symbol Description 7 - reserved 6 SUSPENDM Suspend LOW: Active LOW PHY suspend. Places the ...
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NXP Semiconductors Table 27. Interface Control register (address R = 07h to 09h 07h 08h 09h) bit description Bit Symbol Description 7 INTF_PROT_DIS Interface Protect Disable: Controls circuitry built into the ISP1506 to protect ...
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NXP Semiconductors Table 29. OTG Control register (address R = 0Ah to 0Ch 0Ah 0Bh 0Ch) bit description Bit Symbol Description 7 USE_EXT_ Use External V VBUS_IND 0b — Use the internal OTG comparator ...
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NXP Semiconductors Table 31. USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh 0Dh 0Eh 0Fh) bit description Bit Symbol Description reserved 4 ID_GND_R ID Ground Rise: ...
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NXP Semiconductors Table 34. USB Interrupt Status register (address R = 13h) bit allocation Bit 7 Symbol reserved Reset X Access R Table 35. USB Interrupt Status register (address R = 13h) bit description Bit Symbol Description ...
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NXP Semiconductors 10.1.9 Debug register The bit allocation of the Debug register is given in current value of signals useful for debugging. Table 38. Debug register (address R = 15h) bit allocation Bit 7 Symbol Reset 0 Access R Table ...
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NXP Semiconductors Table 42. Power Control register (address R = 3Dh to 3Fh 3Dh 3Eh 3Fh) bit description Bit Symbol Description reserved; the link must never write logic 1 to ...
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NXP Semiconductors 11. ElectroStatic Discharge (ESD) 11.1 ESD protection The pins that are connected to the USB connector (DP, DM, ID, V minimum ESD protection. Capacitors 0.1 F and 1 F must be connected in parallel from ...
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NXP Semiconductors 12. Limiting values Table 43. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input/output supply CC(I/O) voltage V input voltage I V electrostatic discharge ESD voltage I ...
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NXP Semiconductors 14. Static characteristics Table 45. Static characteristics: supply pins CC(I/O) Typical values are 3 Symbol Parameter ...
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NXP Semiconductors Table 46. Static characteristics: digital pins (CLOCK, DIR, STP, NXT, DATA[3:0], RESET_N/PSW_N CC(I/O) Typical values are 3 ...
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NXP Semiconductors Table 48. Static characteristics: analog I/O pins (DP CC(I/O) Typical values are 3 Symbol Parameter ...
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NXP Semiconductors Table 49. Static characteristics: charge pump CC(I/O) Typical values are 3 Symbol Parameter Voltage V output ...
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NXP Semiconductors Table 53. Static characteristics: resistor reference CC(I/O) Typical values are 3 Symbol Parameter V output voltage ...
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... +25 C; unless otherwise specified. CC(I/O) amb Conditions 4 capacitor each on pins REG1V8 and REG3V3 ISP1506ABS ISP1506BBS ISP1506ABS ISP1506BBS applicable only when clock is applied on pin XTAL1 only for square wave input only for square wave input only for square wave input ...
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NXP Semiconductors Table 55. Dynamic characteristics: digital I/O pins CC(I/O) Symbol Parameter t DATA set-up time with respect to su(DATA) the rising edge of ...
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NXP Semiconductors Table 56. Dynamic characteristics: analog I/O pins (DP and CC(I/O) Symbol Parameter t driver disable delay from PHZ HIGH level t ...
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NXP Semiconductors CONTROL IN DATA IN CONTROL OUT (DIR, NXT) DATA OUT Fig 30. ULPI timing interface ISP1506A_ISP1506B_2 Product data sheet CLOCK t t su(STP) h(STP) (STP su(DATA) h(DATA) (8-BIT) (8-BIT) Rev. 02 — 28 August 2008 ISP1506A; ...
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NXP Semiconductors 16. Application information Table 57. Recommended bill of materials [1] Designator Application C highly recommended for bypass all applications C charge pump is used cp(C_A)-(C_B) C highly recommended for filter all applications C mandatory for peripherals VBUS mandatory ...
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V BUS USB MICRO-AB GND RECEPTACLE IP4359CX4/LF SHIELD SHIELD 7 SHIELD 8 SHIELD 9 C VBUS (1) Frequency is version dependent: ISP1506A: 19.2 MHz; ISP1506B: 26 MHz. ...
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IN +3 pullup CHARGE PUMP ON V BUS USB MICRO-AB GND RECEPTACLE SHIELD 6 IP4359CX4/LF SHIELD ESD SHIELD 8 SHIELD 9 (1) Frequency is ...
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pullup FAULT V BUS SWITCH OUT ON V BUS USB 3 STANDARD-A RECEPTACLE A1 A3 GND 4 IP4359CX4/LF SHIELD SHIELD 6 C VBUS C bypass (1) Frequency is version ...
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V BUS USB STANDARD-B RECEPTACLE GND SHIELD 5 IP4359CX4/ SHIELD 6 D ESD C bypass (1) Frequency is version dependent: ISP1506A: 19.2 MHz; ISP1506B: 26 MHz. Fig 34. Using the ...
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NXP Semiconductors 17. Package outline HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 0.85 mm terminal 1 index area terminal 1 24 index area ...
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NXP Semiconductors 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 18.1 Introduction ...
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NXP Semiconductors 18.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including ...
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NXP Semiconductors Fig 36. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 19. Abbreviations Table 60. Acronym ASIC ATX CD-RW EOP ESD ESR FS ...
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NXP Semiconductors Table 60. Acronym POR RXCMD SE0 SOF SRP SYNC TTL TXCMD USB USB-IF ULPI UTMI UTMI+ 20. References [1] Universal Serial Bus Specification Rev. 2.0 [2] On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 [3] UTMI+ Low ...
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NXP Semiconductors 21. Revision history Table 61. Revision history Document ID Release date ISP1506A_ISP1506B_2 20080828 • Modifications: Globally changed mini-USB, mini-A and mini-B connectors to micro-USB, micro-A and micro-B connectors, respectively. • Section 8.2 “USB and OTG state • Figure ...
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NXP Semiconductors 22. Legal information 22.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
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NXP Semiconductors 24. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Pin description . . . . . . . ...
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NXP Semiconductors 25. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 2. Pin configuration ...
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NXP Semiconductors 26. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...
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NXP Semiconductors 10.1.1 Vendor ID and Product ID registers . . . . . . . . 45 10.1.1.1 Vendor ID Low register . . . . . . . . . . . . . . . . . ...