ISP1506ABS STEricsson, ISP1506ABS Datasheet - Page 11

• Manufacturer Part Number: ISP1506ABS
• Manufacturer: STEricsson

Specifications of ISP1506ABS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
ISP1506A_ISP1506B_2
Product data sheet
7.9.1 DATA[3:0]
7.9.2 V
7.7 Band gap reference voltage
7.8 Power-On Reset (POR)
7.9 Detailed description of pins
which also shows a typical OTG V
amount of current drive required. If the internal charge pump is not used, the C
capacitor is not required.
For details on the C_A and C_B pins, see
The band gap circuit provides a stable internal voltage reference to bias the analog
circuitry. The band gap requires an accurate external reference resistor R
between the RREF and GND pins. For details, see
The ISP1506 has an internal power-on-reset circuit that resets all internal logic on
power-up. The ULPI interface is also reset on power-up.
Remark: When CLOCK starts toggling after power-up, the USB link must issue a reset
command over the ULPI bus to ensure correct operation of the ISP1506.
The ISP1506 is a Physical layer (PHY) containing a USB transceiver. DATA[7:0] is a
dual-edge bidirectional data bus. The USB link must drive DATA[3:0] to LOW when the
ULPI bus is idle. When the link has data to transmit to the PHY, it drives a nonzero value.
The data bus can be reconfigured to carry various data types, as given in
Section
The input power pin that sets the I/O voltage level. For details, see
and
Fig 3.
•
•
•
•
•
CC(I/O)
CLOCK
DATA[3:0]
DIR
NXT
RESET_N/PSW_N
Section
9.
External capacitors connection
16. V
CC(I/O)
Rev. 02 — 28 August 2008
provides power to on-chip pads of the following pins:
ISP1506
V
C_B
C_A
BUS
BUS
load. The value of C
Section
0.1 F
C cp(C_A)-(C_B)
ISP1506A; ISP1506B
7.9.7.
Section
4.7 F
004aaa600
OTG V
ULPI HS USB OTG transceiver
cp(C_A)-(C_B)
16.
BUS
Section
depends on the
© NXP B.V. 2008. All rights reserved.
RREF
Section 8
12,
cp(C_A)-(C_B)
Section 13
connected
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and