ISP1506ABS STEricsson, ISP1506ABS Datasheet - Page 53

• Manufacturer Part Number: ISP1506ABS
• Manufacturer: STEricsson

Specifications of ISP1506ABS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
Table 42.
ISP1506A_ISP1506B_2
Product data sheet
Bit
7 to 4 -
3
2
1
0
Symbol
BVALID_FALL
BVALID_RISE
reserved
IGNORE_RESET
Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit description
10.2 Extended register set
Addresses 00h to 3Fh of the extended register set directly map to the immediate set. This
means a read, write, set or clear operation to these extended addresses will operate on
the immediate register set.
Addresses 40h to FFh are not implemented. Operating on these addresses may result in
undefined behavior of the PHY.
Description
reserved; the link must never write logic 1 to these bits
BVALID Fall: Enables RXCMDs for HIGH-to-LOW transitions on BVALID. When BVALID
changes from HIGH to LOW, the ISP1506 will send an RXCMD to the link with the ALT_INT bit
set to logic 1.
This bit is optional and is not necessary for OTG devices. This bit is provided for debugging
purposes. The session valid comparator should be used instead.
BVALID Rise: Enables RXCMDs for LOW-to-HIGH transitions on BVALID. When BVALID
changes from LOW to HIGH, the ISP1506 will send an RXCMD to the link with the ALT_INT bit
set to logic 1.
This bit is optional and is not necessary for OTG devices. This bit is provided for debugging
purposes. The session valid comparator should be used instead.
-
Ignore Reset: Selects between the RESET_N and PSW_N functions of the RESET_N/PSW_N
pin. The link must set this bit to logic 1 if PSW_N is used in a ganged mode configuration.
0b — The RESET_N/PSW_N pin behaves as an active-LOW reset input (RESET_N) (default).
1b — The RESET_N/PSW_N pin behaves as an active-LOW power switch output (PSW_N).
Rev. 02 — 28 August 2008
ISP1506A; ISP1506B
ULPI HS USB OTG transceiver
© NXP B.V. 2008. All rights reserved.
52 of 79