SGTL5000XNAA3R2 Freescale, SGTL5000XNAA3R2 Datasheet - Page 30

• Manufacturer Part Number: SGTL5000XNAA3R2
• Manufacturer: Freescale

Specifications of SGTL5000XNAA3R2

• Single Supply Voltage (typ): 1.8/2.5/3.3V
• Lead Free Status / RoHS Status: Compliant

Table 16. CHIP_CLK_CTRL 0x0004
30
SGTL500
FUNCTIONAL DEVICE OPERATION
PROGRAMMING EXAMPLES
BITS
15:6
5:4
3:2
1:0
15
14
RATE_MODE
MCLK_FREQ
SYS_FS
FIELD
RSVD
13
12
RW
RW
RW
RW
RO
11
RESET
RSVD
0x0
0x0
0x2
0x0
10
Reserved
Sets the sample rate mode. MCLK_FREQ is still specified relative to the rate in SYS_FS
0x0 = SYS_FS specifies the rate
0x1 = Rate is 1/2 of the SYS_FS rate
0x2 = Rate is 1/4 of the SYS_FS rate
0x3 = Rate is 1/6 of the SYS_FS rate
Sets the internal system sample rate
0x0 = 32 kHz
0x1 = 44.1 kHz
0x2 = 48 kHz
0x3 = 96 kHz
Identifies incoming SYS_MCLK frequency and if the PLL should be used
0x0 = 256*Fs
0x1 = 384*Fs
0x2 = 512*Fs
0x3 = Use PLL
The 0x3 (Use PLL) setting must be used if the SYS_MCLK is not a standard multiple of Fs
(256, 384, or 512). This setting can also be used if SYS_MCLK is a standard multiple of Fs.
Before this field is set to 0x3 (Use PLL), the PLL must be powered up by setting
CHIP_ANA_POWER->PLL_POWERUP and CHIP_ANA_POWER-
>VCOAMP_POWERUP. Also, the PLL dividers must be calculated based on the external
MCLK rate and CHIP_PLL_CTRL register must be set (see CHIP_PLL_CTRL register
description details on how to calculate the divisors).
9
8
7
6
DEFINITION
RATE_MODE
5
Analog Integrated Circuit Device Data
4
3
SYS_FS
Freescale Semiconductor
2
MCLK_FREQ
1
0