MT45V512KW16PEGA-70 WT Micron Technology Inc, MT45V512KW16PEGA-70 WT Datasheet - Page 13

• Manufacturer Part Number: MT45V512KW16PEGA-70 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45V512KW16PEGA-70 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Figure 8:
Deep Power-Down Operation
PDF: 09005aef82f264f6/Source: 09005aef82f264aa
8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. C 4/08 EN
Software Access PAR Functionality
Deep power-down (DPD) operation disables all refresh-related activity. This mode is
used when the system does not require the storage provided by the PSRAM device. Any
stored data will become corrupted upon entering DPD. When refresh activity has been
re-enabled, the PSRAM device will require 150µs to perform an initialization procedure
before normal operations can resume. READ and WRITE operations are ignored during
DPD operation.
The device can only enter DPD if the sleep bit in the CR has been set LOW (CR[4] = 0).
DPD is initiated by bringing ZZ# to the LOW state for longer than 10µs. Returning ZZ# to
HIGH will cause the device to exit DPD and begin a 150µs initialization process. During
this time, the current consumption will be higher than the specified standby levels, but
considerably lower than the active current specification.
Driving ZZ# LOW puts the device in PAR mode if the SLEEP bit in the CR has been set
HIGH (CR[4] = 1).
The device should not be put into DPD using the CR software-access sequence.
No
PAR permanently
To enable PAR,
Software LOAD
bring ZZ# LOW
Change to ZZ#
functionality;
independent
of ZZ# level
executed?
Power-up
enabled,
for 10µs
Yes
8Mb: 3.0V Core Async/Page PSRAM Memory 512K x 16
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Low-Power Operation
©2007 Micron Technology, Inc. All rights reserved.